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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [io/] [ip/] [io_ps2/] [rtl/] [verilog/] [top.body.mouse] - Blame information for rev 131

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parameter PS2_DATA      = 4'h0;
parameter STATUS        = 4'h2;
parameter CNTRL         = 4'h4;
parameter X_POS         = 4'h6;
parameter Y_POS         = 4'h8;
 
 
 
 
`VARIANT`MICRO_REG
ps2_micro_reg
(
   .clk                ( clk              ),
   .reset              ( reset            ),
   .enable             ( enable           ),
   .cs                 ( cs               ),
   .wr                 ( wr               ),
   .rd                 ( rd               ),
   .byte_lanes         ( 1'b1             ),
   .addr               ( addr[3:0]        ),
   .wdata              ( wdata[7:0]       ),
   .rdata              ( rdata            ),
 
   .ps2_data_cs    (),
   .wdata_buf_cs (),
   .wdata_buf_dec (),
   .wdata_buf_wr_0 (),
   .status_cs (),
   .status_dec (),
   .cntrl_cs (),
   .cntrl_dec (),
   .cntrl_wr_0 (),
 
   .x_pos_cs (),
   .x_pos_dec (),
 
   .y_pos_cs (),
   .y_pos_dec (),
 
 
 
 
   .ps2_data_rdata     ( rcv_data         ),
   .ps2_data_dec       ( ps2_data_rd      ),
   .status_rdata       ({!buffer_empty   ,
                          rcv_data_avail ,
                          busy           ,
                          rx_parity_error,
                          rx_parity_rcv  ,
                          rx_parity_cal  ,
                          rx_frame_error ,
                          tx_ack_error }  ),
   .x_pos_rdata        ( x_pos[7:0]       ),
   .y_pos_rdata        ( y_pos[7:0]       ),
   .cntrl              ( cntrl            ),
   .cntrl_rdata        ( cntrl            ),
   .next_cntrl         ( cntrl            ),
   .wdata_buf          ( wdata_buf        ),
   .next_wdata_buf     ( wdata_buf        )
);
 
 
assign   ps2_rx_clear      = cntrl[0] ? read :rd && cs && enable && ps2_data_rd;
assign        poll_enable  =   cntrl[0];
 
always@(posedge clk)
if (reset)
  begin
    ps2_data_read_stb <= 1'b0;
   end
else
  begin
   ps2_data_read_stb  <= (  enable &&  ps2_data_rd && rd );
  end
 
 
 
 
   always@(posedge clk )
     if(reset || (!poll_enable))
       begin
       byt_cntr       <= 2'b00;
       new_packet     <= 1'b0;
       end
     else
     if(read)
       begin
     byt_cntr       <= byt_cntr + 2'b01;
     new_packet     <= 1'b0;
     end
     else
     if (byt_cntr == 2'b11)
       begin
         byt_cntr       <= 2'b00;
         new_packet     <= 1'b1;
       end
     else
       begin
       byt_cntr       <= byt_cntr;
       new_packet     <= 1'b0;
       end
 
 
 
 
     always@(posedge  clk)
     if( reset  || (!poll_enable) )
           begin
           ms_y_ovf   <= 1'b0;
           ms_x_ovf   <= 1'b0;
           ms_y_sign  <= 1'b0;
           ms_x_sign  <= 1'b0;
           ms_one     <= 1'b1;
           ms_mid     <= 1'b0;
           ms_right   <= 1'b0;
           ms_left    <= 1'b0;
           x_pos      <= 10'h000;
           y_pos      <= 10'h000;
        end
     else
         if( read)
           begin
                if (byt_cntr == 2'b00)  {ms_y_ovf,ms_x_ovf,ms_y_sign,ms_x_sign,ms_one,ms_mid,ms_right,ms_left} <= rcv_data;
                else
        if (byt_cntr == 2'b01)   x_pos            <= x_pos +   {ms_x_sign,ms_x_sign,rcv_data};
                else
        if (byt_cntr == 2'b10)   y_pos            <= y_pos -   {ms_y_sign,ms_y_sign,rcv_data};
                else
                 begin
                    x_pos  <= x_pos;
                    y_pos  <= y_pos;
                 end
 
           end
         else
                    begin
                    x_pos  <= x_pos;
                    y_pos  <= y_pos;
                 end
 
 
 
 

Line No.	Rev	Author	Line
1	131	jt_eaton	`parameter PS2_DATA = 4'h0;`
2			`parameter STATUS = 4'h2;`
3			`parameter CNTRL = 4'h4;`
4			`parameter X_POS = 4'h6;`
5			`parameter Y_POS = 4'h8;`
6
7
8
9
10			`VARIANT`MICRO_REG
11			`ps2_micro_reg`
12			`(`
13			`.clk ( clk ),`
14			`.reset ( reset ),`
15			`.enable ( enable ),`
16			`.cs ( cs ),`
17			`.wr ( wr ),`
18			`.rd ( rd ),`
19			`.byte_lanes ( 1'b1 ),`
20			`.addr ( addr[3:0] ),`
21			`.wdata ( wdata[7:0] ),`
22			`.rdata ( rdata ),`
23
24			`.ps2_data_cs (),`
25			`.wdata_buf_cs (),`
26			`.wdata_buf_dec (),`
27			`.wdata_buf_wr_0 (),`
28			`.status_cs (),`
29			`.status_dec (),`
30			`.cntrl_cs (),`
31			`.cntrl_dec (),`
32			`.cntrl_wr_0 (),`
33
34			`.x_pos_cs (),`
35			`.x_pos_dec (),`
36
37			`.y_pos_cs (),`
38			`.y_pos_dec (),`
39
40
41
42
43			`.ps2_data_rdata ( rcv_data ),`
44			`.ps2_data_dec ( ps2_data_rd ),`
45			`.status_rdata ({!buffer_empty ,`
46			`rcv_data_avail ,`
47			`busy ,`
48			`rx_parity_error,`
49			`rx_parity_rcv ,`
50			`rx_parity_cal ,`
51			`rx_frame_error ,`
52			`tx_ack_error } ),`
53			`.x_pos_rdata ( x_pos[7:0] ),`
54			`.y_pos_rdata ( y_pos[7:0] ),`
55			`.cntrl ( cntrl ),`
56			`.cntrl_rdata ( cntrl ),`
57			`.next_cntrl ( cntrl ),`
58			`.wdata_buf ( wdata_buf ),`
59			`.next_wdata_buf ( wdata_buf )`
60			`);`
61
62
63			`assign ps2_rx_clear = cntrl[0] ? read :rd && cs && enable && ps2_data_rd;`
64			`assign poll_enable = cntrl[0];`
65
66			`always@(posedge clk)`
67			`if (reset)`
68			`begin`
69			`ps2_data_read_stb <= 1'b0;`
70			`end`
71			`else`
72			`begin`
73			`ps2_data_read_stb <= ( enable && ps2_data_rd && rd );`
74			`end`
75
76
77
78
79			`always@(posedge clk )`
80			`if(reset \|\| (!poll_enable))`
81			`begin`
82			`byt_cntr <= 2'b00;`
83			`new_packet <= 1'b0;`
84			`end`
85			`else`
86			`if(read)`
87			`begin`
88			`byt_cntr <= byt_cntr + 2'b01;`
89			`new_packet <= 1'b0;`
90			`end`
91			`else`
92			`if (byt_cntr == 2'b11)`
93			`begin`
94			`byt_cntr <= 2'b00;`
95			`new_packet <= 1'b1;`
96			`end`
97			`else`
98			`begin`
99			`byt_cntr <= byt_cntr;`
100			`new_packet <= 1'b0;`
101			`end`
102
103
104
105
106			`always@(posedge clk)`
107			`if( reset \|\| (!poll_enable) )`
108			`begin`
109			`ms_y_ovf <= 1'b0;`
110			`ms_x_ovf <= 1'b0;`
111			`ms_y_sign <= 1'b0;`
112			`ms_x_sign <= 1'b0;`
113			`ms_one <= 1'b1;`
114			`ms_mid <= 1'b0;`
115			`ms_right <= 1'b0;`
116			`ms_left <= 1'b0;`
117			`x_pos <= 10'h000;`
118			`y_pos <= 10'h000;`
119			`end`
120			`else`
121			`if( read)`
122			`begin`
123			`if (byt_cntr == 2'b00) {ms_y_ovf,ms_x_ovf,ms_y_sign,ms_x_sign,ms_one,ms_mid,ms_right,ms_left} <= rcv_data;`
124			`else`
125			`if (byt_cntr == 2'b01) x_pos <= x_pos + {ms_x_sign,ms_x_sign,rcv_data};`
126			`else`
127			`if (byt_cntr == 2'b10) y_pos <= y_pos - {ms_y_sign,ms_y_sign,rcv_data};`
128			`else`
129			`begin`
130			`x_pos <= x_pos;`
131			`y_pos <= y_pos;`
132			`end`
133
134			`end`
135			`else`
136			`begin`
137			`x_pos <= x_pos;`
138			`y_pos <= y_pos;`
139			`end`
140
141
142
143

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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [io/] [ip/] [io_ps2/] [rtl/] [verilog/] [top.body.mouse] - Blame information for rev 131