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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [io/] [ip/] [io_ps2/] [rtl/] [xml/] [io_ps2_def.xml] - Blame information for rev 131

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xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
 
opencores.org
io
io_ps2
def  default
 
 

 
 slave_clk
  
  
  
    
      
        clk
        clk
      
    
 
 
 
 slave_reset
  
  
  
    
      
        reset
        reset
      
    
 
 
 
mb
   
   
   little
   8
     
     
        
         rdata
         
         rdata
           wire
           70
         
       
 
        
         addr
         
         addr
           30
         
       
 
 
        
         wdata
         
         wdata
           70
         
       
 
 
        
         rd
         
         rd
         
       
 
        
         wr
         
         wr
         
       
 
        
         cs
         
         cs
         
       
 
      
  
 
 

 
 
 

 
 
 
 
 
 
 
 

  gen_registers
  103.0
  common
  none
  ./tools/regtool/gen_registers
    
    
      bus_intf
      mb
    
    
      dest_dir
      ../verilog
    
  

 
 
 

  gen_verilog
  104.0
  none
  common
  ./tools/verilog/gen_verilog
  
    
      destination
      top
    
    
      dest_dir
      ../verilog
    
  

 
 
 

 
 
 
  
 
    
      fs-common
 
      
        
        ../verilog/top.body
        verilogSourcefragment
      
 
    
 
 
    
      fs-sim
 
      
        
        ../verilog/copyright.v
        verilogSourceinclude
      
 
      
        
        ../verilog/common/top
        verilogSourcemodule
      
 
      
        mb
        ../verilog/io_ps2_def_mb
        verilogSourcemodule
      
 
 
 
    
 
 
 
    
      fs-syn
 
 
      
        
        ../verilog/copyright.v
        verilogSourceinclude
      
 
      
        
        ../verilog/common/top
        verilogSourcemodule
      
 
      
        mb
        ../verilog/io_ps2_def_mb
        verilogSourcemodule
      
 
 
 
 
 
    
 
 
 
 
  
 
 
 
 
 

       
 
              
              Hierarchical
 
              
                                   spirit:library="io"
                                   spirit:name="io_ps2"
                                   spirit:version="def.design"/>
              
 
 
              
              verilog
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="verilog"/>
              
              
 
 
 
 
 
              
              commoncommon
              Verilog
              
                     
                            fs-common
                     
              
 
              
              sim:*Simulation:*
              Verilog
              
                     
                            fs-sim
                     
              
 
 
              
              syn:*Synthesis:*
              Verilog
              
                     
                            fs-syn
                     
              
 
 
              
              doc
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="documentation"/>
              
              :*Documentation:*
              Verilog
              
 
 
 
      
 
 
 
 
 

 
 
enable
wire
in

 
 
 
rcv_data_avail
wire
out

 
 
 
 

 

 
 
 
 


 mb
8

 mb
 0x00
 
  
  mb_microbus
  0x10
  8
 
 
 
   ps2_data
   0x0
   8
   read-only
  
 
 
   wdata_buf
   0x0
   8
   write-only
  
 
 
   status
   0x2
   8
   read-only
  
 
 
   cntrl
   0x4
   8
   read-write
  
 
 
 
 
  
 
 

 

 
 
 


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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [io/] [ip/] [io_ps2/] [rtl/] [xml/] [io_ps2_def.xml] - Blame information for rev 131

Line No.	Rev	Author	Line
1	131	jt_eaton
2
30
31			`xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"`
32			`xmlns:socgen="http://opencores.org"`
33			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
34			`xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009`
35			`http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">`
36
37			`opencores.org`
38			`io`
39			`io_ps2`
40			`def default`
41
42
43
44
45			`slave_clk`
46
47
48
49
50
51			`clk`
52			`clk`
53
54
55
56
57
58			`slave_reset`
59
60
61
62
63
64			`reset`
65			`reset`
66
67
68
69
70
71			`mb`
72
73
74			`little`
75			`8`
76
77
78
79			`rdata`
80
81			`rdata`
82			`wire`
83			`70`
84
85
86
87
88			`addr`
89
90			`addr`
91			`30`
92
93
94
95
96
97			`wdata`
98
99			`wdata`
100			`70`
101
102
103
104
105
106			`rd`
107
108			`rd`
109
110
111
112
113			`wr`
114
115			`wr`
116
117
118
119
120			`cs`
121
122			`cs`
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144			`gen_registers`
145			`103.0`
146			`common`
147			`none`
148			`./tools/regtool/gen_registers`
149
150
151			`bus_intf`
152			`mb`
153
154
155			`dest_dir`
156			`../verilog`
157
158
159
160
161
162
163
164			`gen_verilog`
165			`104.0`
166			`none`
167			`common`
168			`./tools/verilog/gen_verilog`
169
170
171			`destination`
172			`top`
173
174
175			`dest_dir`
176			`../verilog`
177
178
179
180
181
182
183
184
185
186
187
188
189
190			`fs-common`
191
192
193
194			`../verilog/top.body`
195			`verilogSourcefragment`
196
197
198
199
200
201
202			`fs-sim`
203
204
205
206			`../verilog/copyright.v`
207			`verilogSourceinclude`
208
209
210
211
212			`../verilog/common/top`
213			`verilogSourcemodule`
214
215
216
217			`mb`
218			`../verilog/io_ps2_def_mb`
219			`verilogSourcemodule`
220
221
222
223
224
225
226
227
228
229			`fs-syn`
230
231
232
233
234			`../verilog/copyright.v`
235			`verilogSourceinclude`
236
237
238
239
240			`../verilog/common/top`
241			`verilogSourcemodule`
242
243
244
245			`mb`
246			`../verilog/io_ps2_def_mb`
247			`verilogSourcemodule`
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269			`Hierarchical`
270
271
272			`spirit:library="io"`
273			`spirit:name="io_ps2"`
274			`spirit:version="def.design"/>`
275
276
277
278
279			`verilog`
280
281
282			`spirit:library="Testbench"`
283			`spirit:name="toolflow"`
284			`spirit:version="verilog"/>`
285
286
287
288
289
290
291
292
293			`commoncommon`
294			`Verilog`
295
296
297			`fs-common`
298
299
300
301
302			`sim:Simulation:`
303			`Verilog`
304
305
306			`fs-sim`
307
308
309
310
311
312			`syn:Synthesis:`
313			`Verilog`
314
315
316			`fs-syn`
317
318
319
320
321
322			`doc`
323
324
325			`spirit:library="Testbench"`
326			`spirit:name="toolflow"`
327			`spirit:version="documentation"/>`
328
329			`:Documentation:`
330			`Verilog`
331
332
333
334
335
336
337
338
339
340
341
342
343
344			`enable`
345			`wire`
346			`in`
347
348
349
350
351			`rcv_data_avail`
352			`wire`
353			`out`
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368			`mb`
369			`8`
370
371			`mb`
372			`0x00`
373
374
375			`mb_microbus`
376			`0x10`
377			`8`
378
379
380
381			`ps2_data`
382			`0x0`
383			`8`
384			`read-only`
385
386
387
388			`wdata_buf`
389			`0x0`
390			`8`
391			`write-only`
392
393
394
395			`status`
396			`0x2`
397			`8`
398			`read-only`
399
400
401
402			`cntrl`
403			`0x4`
404			`8`
405			`read-write`
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420