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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [io/] [ip/] [io_timer/] [rtl/] [verilog/] [top.body] - Blame information for rev 131

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parameter TIMER_0_START  = 4'h0;
parameter TIMER_0_COUNT  = 4'h2;
parameter TIMER_0_END    = 4'h4;
 
parameter TIMER_1_START  = 4'h8;
parameter TIMER_1_COUNT  = 4'hA;
parameter TIMER_1_END    = 4'hC;
 
 
 
 
 
parameter IDLE         = 3'b001;
parameter RUNNING      = 3'b010;
parameter TRIGGERED    = 3'b100;
 
 
 
 
reg [7:0] count_0;
reg [2:0] state_0;
 
reg [7:0] count_1;
reg [2:0] state_1;
 
 
wire [7:0] timer_0;
wire [7:0] timer_1;
 
`VARIANT`MB
io_module_timer_micro_reg
(
  .clk             ( clk           ),
  .reset           ( reset         ),
  .cs              ( cs            ),
  .enable          ( enable        ),
  .wr              ( wr            ),
  .rd              ( rd            ),
  .byte_lanes      ( 1'b1          ),
  .addr            ( addr          ),
  .wdata           ( wdata         ),
  .rdata           ( rdata         ),
 
  .timer_0_end       ( timer_0       ),
  .next_timer_0_end  ( timer_0       ),
  .timer_0_start_cs  (               ),
  .timer_0_start_dec (               ),
  .timer_0_count_cs  (               ),
  .timer_0_count_dec (               ),
  .timer_0_end_cs    (               ),
  .timer_0_end_dec   (               ),
  .timer_0_end_wr_0  (               ),
  .timer_0_start_rdata   ({4'h0,irq[0],state_0[2:0]} ),
  .timer_0_count_rdata   ( count_0                   ),
 
 
  .timer_1_end       ( timer_1       ),
  .next_timer_1_end  ( timer_1       ),
  .timer_1_start_cs  (               ),
  .timer_1_start_dec (               ),
  .timer_1_count_cs  (               ),
  .timer_1_count_dec (               ),
  .timer_1_end_cs    (               ),
  .timer_1_end_dec   (               ),
  .timer_1_end_wr_0  (               ),
  .timer_1_start_rdata   ({4'h0,irq[1],state_1[2:0]} ),
  .timer_1_count_rdata   ( count_1                   )
);
 
 
 
 
 
 
 
always@(posedge clk)
if(reset)
  begin
  irq <= 2'b00;
  end
else
  begin
  irq <= {state_1[2],state_0[2]};
  end
 
 
 
 
always@(posedge clk)
if (reset)
  begin
  state_0 <= IDLE;
  count_0 <= 8'h00;
  end
else
case (state_0)
     (IDLE):
 
     if(wr && enable  && cs && addr[3:0] == TIMER_0_START)
         begin
         state_0 <= RUNNING;
         count_0 <= wdata;
 end
     else
         begin
         state_0 <= IDLE;
         count_0 <= 8'h00;
 end
 
     (RUNNING):
      if( count_0 == 8'h00)
         begin
         state_0 <= TRIGGERED;
         count_0 <= 8'h00;
         end
      else
         begin
         state_0 <= RUNNING;
         count_0 <=  count_0 -8'h01;
 end
 
     (TRIGGERED):
     if(wr && enable && cs && addr[3:0] == TIMER_0_END)
         begin
         state_0 <= IDLE;
         count_0 <= 8'h00;
 end
     else
         begin
         state_0 <= TRIGGERED;
         count_0 <= 8'h00;
 end
 
     default:
          begin
          state_0 <= IDLE;
          count_0 <= 8'h00;
          end
endcase // case (state_0)
 
 
 
 
 
always@(posedge clk)
if (reset)
  begin
  state_1 <= IDLE;
  count_1 <= 8'h00;
  end
else
case (state_1)
     (IDLE):
 
     if(wr && enable && cs && addr[3:0] == TIMER_1_START)
         begin
         state_1 <= RUNNING;
         count_1 <= wdata;
 end
     else
         begin
         state_1 <= IDLE;
         count_1 <= 8'h00;
 end
 
     (RUNNING):
      if( count_1 == 8'h00)
         begin
         state_1 <= TRIGGERED;
         count_1 <= 8'h00;
         end
      else
         begin
         state_1 <= RUNNING;
         count_1 <=  count_1 -8'h01;
 end
 
     (TRIGGERED):
     if(wr && enable && cs && addr[3:0] == TIMER_1_END)
         begin
         state_1 <= IDLE;
         count_1 <= 8'h00;
 end
     else
         begin
         state_1 <= TRIGGERED;
         count_1 <= 8'h00;
 end
 
     default:
          begin
          state_1 <= IDLE;
          count_1 <= 8'h00;
          end
endcase
 
 
 
 

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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [io/] [ip/] [io_timer/] [rtl/] [verilog/] [top.body] - Blame information for rev 131

Line No.	Rev	Author	Line
1	131	jt_eaton
2
3			`parameter TIMER_0_START = 4'h0;`
4			`parameter TIMER_0_COUNT = 4'h2;`
5			`parameter TIMER_0_END = 4'h4;`
6
7			`parameter TIMER_1_START = 4'h8;`
8			`parameter TIMER_1_COUNT = 4'hA;`
9			`parameter TIMER_1_END = 4'hC;`
10
11
12
13
14
15			`parameter IDLE = 3'b001;`
16			`parameter RUNNING = 3'b010;`
17			`parameter TRIGGERED = 3'b100;`
18
19
20
21
22			`reg [7:0] count_0;`
23			`reg [2:0] state_0;`
24
25			`reg [7:0] count_1;`
26			`reg [2:0] state_1;`
27
28
29			`wire [7:0] timer_0;`
30			`wire [7:0] timer_1;`
31
32			`VARIANT`MB
33			`io_module_timer_micro_reg`
34			`(`
35			`.clk ( clk ),`
36			`.reset ( reset ),`
37			`.cs ( cs ),`
38			`.enable ( enable ),`
39			`.wr ( wr ),`
40			`.rd ( rd ),`
41			`.byte_lanes ( 1'b1 ),`
42			`.addr ( addr ),`
43			`.wdata ( wdata ),`
44			`.rdata ( rdata ),`
45
46			`.timer_0_end ( timer_0 ),`
47			`.next_timer_0_end ( timer_0 ),`
48			`.timer_0_start_cs ( ),`
49			`.timer_0_start_dec ( ),`
50			`.timer_0_count_cs ( ),`
51			`.timer_0_count_dec ( ),`
52			`.timer_0_end_cs ( ),`
53			`.timer_0_end_dec ( ),`
54			`.timer_0_end_wr_0 ( ),`
55			`.timer_0_start_rdata ({4'h0,irq[0],state_0[2:0]} ),`
56			`.timer_0_count_rdata ( count_0 ),`
57
58
59			`.timer_1_end ( timer_1 ),`
60			`.next_timer_1_end ( timer_1 ),`
61			`.timer_1_start_cs ( ),`
62			`.timer_1_start_dec ( ),`
63			`.timer_1_count_cs ( ),`
64			`.timer_1_count_dec ( ),`
65			`.timer_1_end_cs ( ),`
66			`.timer_1_end_dec ( ),`
67			`.timer_1_end_wr_0 ( ),`
68			`.timer_1_start_rdata ({4'h0,irq[1],state_1[2:0]} ),`
69			`.timer_1_count_rdata ( count_1 )`
70			`);`
71
72
73
74
75
76
77
78			`always@(posedge clk)`
79			`if(reset)`
80			`begin`
81			`irq <= 2'b00;`
82			`end`
83			`else`
84			`begin`
85			`irq <= {state_1[2],state_0[2]};`
86			`end`
87
88
89
90
91			`always@(posedge clk)`
92			`if (reset)`
93			`begin`
94			`state_0 <= IDLE;`
95			`count_0 <= 8'h00;`
96			`end`
97			`else`
98			`case (state_0)`
99			`(IDLE):`
100
101			`if(wr && enable && cs && addr[3:0] == TIMER_0_START)`
102			`begin`
103			`state_0 <= RUNNING;`
104			`count_0 <= wdata;`
105			`end`
106			`else`
107			`begin`
108			`state_0 <= IDLE;`
109			`count_0 <= 8'h00;`
110			`end`
111
112			`(RUNNING):`
113			`if( count_0 == 8'h00)`
114			`begin`
115			`state_0 <= TRIGGERED;`
116			`count_0 <= 8'h00;`
117			`end`
118			`else`
119			`begin`
120			`state_0 <= RUNNING;`
121			`count_0 <= count_0 -8'h01;`
122			`end`
123
124			`(TRIGGERED):`
125			`if(wr && enable && cs && addr[3:0] == TIMER_0_END)`
126			`begin`
127			`state_0 <= IDLE;`
128			`count_0 <= 8'h00;`
129			`end`
130			`else`
131			`begin`
132			`state_0 <= TRIGGERED;`
133			`count_0 <= 8'h00;`
134			`end`
135
136			`default:`
137			`begin`
138			`state_0 <= IDLE;`
139			`count_0 <= 8'h00;`
140			`end`
141			`endcase // case (state_0)`
142
143
144
145
146
147			`always@(posedge clk)`
148			`if (reset)`
149			`begin`
150			`state_1 <= IDLE;`
151			`count_1 <= 8'h00;`
152			`end`
153			`else`
154			`case (state_1)`
155			`(IDLE):`
156
157			`if(wr && enable && cs && addr[3:0] == TIMER_1_START)`
158			`begin`
159			`state_1 <= RUNNING;`
160			`count_1 <= wdata;`
161			`end`
162			`else`
163			`begin`
164			`state_1 <= IDLE;`
165			`count_1 <= 8'h00;`
166			`end`
167
168			`(RUNNING):`
169			`if( count_1 == 8'h00)`
170			`begin`
171			`state_1 <= TRIGGERED;`
172			`count_1 <= 8'h00;`
173			`end`
174			`else`
175			`begin`
176			`state_1 <= RUNNING;`
177			`count_1 <= count_1 -8'h01;`
178			`end`
179
180			`(TRIGGERED):`
181			`if(wr && enable && cs && addr[3:0] == TIMER_1_END)`
182			`begin`
183			`state_1 <= IDLE;`
184			`count_1 <= 8'h00;`
185			`end`
186			`else`
187			`begin`
188			`state_1 <= TRIGGERED;`
189			`count_1 <= 8'h00;`
190			`end`
191
192			`default:`
193			`begin`
194			`state_1 <= IDLE;`
195			`count_1 <= 8'h00;`
196			`end`
197			`endcase`
198
199
200
201