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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [io/] [ip/] [io_timer/] [rtl/] [xml/] [io_timer_def.xml] - Blame information for rev 135

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xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014
http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">
 
opencores.org
io
io_timer
def
 
 

 
 slave_clk
  
  
      
  
    
      
        clk
        clk
      
    
        
      
  
 
 
 
 slave_reset
  
  
      
  
    
      
        reset
        reset
      
    
        
      
  
 
 
 
 
mb
   
  
      
   
     
        
         rdata
         
         rdata
           wire
           70
         
       
 
        
         addr
         
         addr
           30
         
       
 
 
        
         wdata
         
         wdata
           70
         
       
 
 
        
         rd
         
         rd
         
       
 
        
         wr
         
         wr
         
       
 
        
         cs
         
         cs
         
       
 
      
 
        
      
 
   little
   8
     
 
  
 
 
 

 
 
 

 
 
 
 
 
 

  gen_registers
  102.1
  :*common:*
  none
  tools/regtool/gen_registers
    
    
      bus_intf
      mb
    
    
      dest_dir
      ../verilog
    
  

 
 
 

  gen_verilog
  104.0
  none
  :*common:*
  tools/verilog/gen_verilog
    
    
      destination
      io_timer_def
    
  

 
 
 
 

 
 
  
 
 
    
 
      fs-common
 
      
        
        ../verilog/top.body
        verilogSourcefragment
      
 
 
    
 
 
 
 
    
 
      fs-sim
 
      
        
        ../verilog/copyright.v
        verilogSourceinclude
      
 
      
        
        ../verilog/common/io_timer_def
        verilogSourcemodule
      
 
      
        mb
        ../verilog/io_timer_def_mb
        verilogSourcemodule
      
 
 
 
    
 
 
 
 
 
  
 
 
 
 
 
 

       
 
 
              
              verilog
              
              
                                   ipxact:library="Testbench"
                                   ipxact:name="toolflow"
                                   ipxact:version="verilog"/>
              
              
 
 
 
 
 
 
              
              common:*common:*
              Verilog
              
                     
                            fs-common
                     
              
 
              
              sim:*Simulation:*
              Verilog
              
                     
                            fs-sim
                     
              
 
              
              syn:*Synthesis:*
              Verilog
              
                     
                            fs-sim
                     
              
 
 
              
              doc
              
              
                                   ipxact:library="Testbench"
                                   ipxact:name="toolflow"
                                   ipxact:version="documentation"/>
              
              :*Documentation:*
              Verilog
              
 
      
 

 
 
enable
wire
in

 
 
 
clk
wire
in

 
 
reset
wire
in

 
 
cs
wire
in

 
 
rd
wire
in

 
wr
wire
in

 
 
addr
wire
in
30

 
 
wdata
wire
in
70

 
 
rdata
wire
out
70

 
 
 
 
 
 
 
irq
reg
out
TIMERS-10

 


 
 
 
 


 mb
8

 mb
 0x00
 
  
  mb_microbus
  0x10
  8
 
 
 
   timer_0_start
   0x0
   8
   read-only
  
 
 
   timer_0_count
   0x2
   8
   read-only
  
 
 
   timer_0_end
   0x4
   8
   write-only
  
 
 
 
   timer_1_start
   0x8
   8
   read-only
  
 
 
   timer_1_count
   0xa
   8
   read-only
  
 
 
   timer_1_end
   0xc
   8
   write-only
  
 
  
 
 

 

 
 
 


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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [io/] [ip/] [io_timer/] [rtl/] [xml/] [io_timer_def.xml] - Blame information for rev 135

Line No.	Rev	Author	Line
1	131	jt_eaton
2
30	135	jt_eaton
31			`xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"`
32	131	jt_eaton	`xmlns:socgen="http://opencores.org"`
33			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
34	135	jt_eaton	`xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014`
35			`http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">`
36	131	jt_eaton
37	135	jt_eaton	`opencores.org`
38			`io`
39			`io_timer`
40			`def`
41	131	jt_eaton
42
43	135	jt_eaton
44	131	jt_eaton
45	135	jt_eaton	`slave_clk`
46
47
48
49
50
51
52			`clk`
53			`clk`
54
55
56
57
58
59
60	131	jt_eaton
61
62	135	jt_eaton	`slave_reset`
63
64
65
66
67
68
69			`reset`
70			`reset`
71
72
73
74
75
76
77	131	jt_eaton
78
79
80	135	jt_eaton	`mb`
81
82
83
84
85
86
87			`rdata`
88
89			`rdata`
90			`wire`
91			`70`
92
93
94
95
96			`addr`
97
98			`addr`
99			`30`
100
101
102
103
104
105			`wdata`
106
107			`wdata`
108			`70`
109
110
111
112
113
114			`rd`
115
116			`rd`
117
118
119
120
121			`wr`
122
123			`wr`
124
125
126
127
128			`cs`
129
130			`cs`
131
132
133
134
135
136
137
138
139			`little`
140			`8`
141
142	131	jt_eaton
143	135	jt_eaton
144	131	jt_eaton
145
146
147	135	jt_eaton
148	131	jt_eaton
149
150
151	135	jt_eaton
152	131	jt_eaton
153
154
155
156
157
158	135	jt_eaton
159			`gen_registers`
160			`102.1`
161			`:common:`
162			`none`
163			`tools/regtool/gen_registers`
164
165
166			`bus_intf`
167			`mb`
168
169
170			`dest_dir`
171			`../verilog`
172
173
174
175	131	jt_eaton
176
177
178	135	jt_eaton
179			`gen_verilog`
180			`104.0`
181			`none`
182			`:common:`
183			`tools/verilog/gen_verilog`
184
185
186			`destination`
187			`io_timer_def`
188
189
190
191	131	jt_eaton
192
193
194
195	135	jt_eaton
196	133	jt_eaton
197	131	jt_eaton
198	135	jt_eaton
199	131	jt_eaton
200
201	135	jt_eaton
202	131	jt_eaton
203	135	jt_eaton	`fs-common`
204	131	jt_eaton
205	135	jt_eaton
206
207			`../verilog/top.body`
208			`verilogSourcefragment`
209
210	131	jt_eaton
211
212	135	jt_eaton
213	131	jt_eaton
214
215
216
217	135	jt_eaton
218	131	jt_eaton
219	135	jt_eaton	`fs-sim`
220	131	jt_eaton
221	135	jt_eaton
222
223			`../verilog/copyright.v`
224			`verilogSourceinclude`
225
226	131	jt_eaton
227	135	jt_eaton
228
229			`../verilog/common/io_timer_def`
230			`verilogSourcemodule`
231
232	131	jt_eaton
233	135	jt_eaton
234			`mb`
235			`../verilog/io_timer_def_mb`
236			`verilogSourcemodule`
237
238	131	jt_eaton
239
240
241	135	jt_eaton
242	131	jt_eaton
243
244
245
246
247	135	jt_eaton
248	131	jt_eaton
249
250
251
252
253
254	135	jt_eaton
255
256	131	jt_eaton
257
258	135	jt_eaton
259			`verilog`
260
261
262			`ipxact:library="Testbench"`
263			`ipxact:name="toolflow"`
264			`ipxact:version="verilog"/>`
265
266
267	131	jt_eaton
268
269
270
271
272
273	135	jt_eaton
274			`common:common:`
275			`Verilog`
276
277
278			`fs-common`
279
280
281	131	jt_eaton
282	135	jt_eaton
283			`sim:Simulation:`
284			`Verilog`
285
286
287			`fs-sim`
288
289
290	131	jt_eaton
291	135	jt_eaton
292			`syn:Synthesis:`
293			`Verilog`
294
295
296			`fs-sim`
297
298
299	131	jt_eaton
300
301	135	jt_eaton
302			`doc`
303
304
305			`ipxact:library="Testbench"`
306			`ipxact:name="toolflow"`
307			`ipxact:version="documentation"/>`
308
309			`:Documentation:`
310			`Verilog`
311
312	131	jt_eaton
313	135	jt_eaton
314	131	jt_eaton
315	135	jt_eaton
316	131	jt_eaton
317
318	135	jt_eaton	`enable`
319			`wire`
320			`in`
321
322	131	jt_eaton
323
324	135	jt_eaton
325			`clk`
326			`wire`
327			`in`
328
329	131	jt_eaton
330
331	135	jt_eaton	`reset`
332			`wire`
333			`in`
334
335	131	jt_eaton
336
337	135	jt_eaton	`cs`
338			`wire`
339			`in`
340
341	131	jt_eaton
342
343	135	jt_eaton	`rd`
344			`wire`
345			`in`
346
347	131	jt_eaton
348	135	jt_eaton	`wr`
349			`wire`
350			`in`
351
352	131	jt_eaton
353
354	135	jt_eaton	`addr`
355			`wire`
356			`in`
357			`30`
358
359	131	jt_eaton
360
361	135	jt_eaton	`wdata`
362			`wire`
363			`in`
364			`70`
365
366	131	jt_eaton
367
368	135	jt_eaton	`rdata`
369			`wire`
370			`out`
371			`70`
372
373	131	jt_eaton
374
375
376
377	135	jt_eaton
378
379
380			`irq`
381			`reg`
382			`out`
383			`TIMERS-10`
384
385
386
387
388
389
390
391
392
393
394			`mb`
395			`8`
396
397			`mb`
398			`0x00`
399	131	jt_eaton
400	135	jt_eaton
401			`mb_microbus`
402			`0x10`
403			`8`
404	131	jt_eaton
405
406	135	jt_eaton
407			`timer_0_start`
408			`0x0`
409			`8`
410			`read-only`
411
412	131	jt_eaton
413	135	jt_eaton
414			`timer_0_count`
415			`0x2`
416			`8`
417			`read-only`
418
419	131	jt_eaton
420	135	jt_eaton
421			`timer_0_end`
422			`0x4`
423			`8`
424			`write-only`
425
426	131	jt_eaton
427
428	135	jt_eaton
429			`timer_1_start`
430			`0x8`
431			`8`
432			`read-only`
433
434	131	jt_eaton
435	135	jt_eaton
436			`timer_1_count`
437			`0xa`
438			`8`
439			`read-only`
440
441	131	jt_eaton
442	135	jt_eaton
443			`timer_1_end`
444			`0xc`
445			`8`
446			`write-only`
447
448	131	jt_eaton
449	135	jt_eaton
450	131	jt_eaton
451
452	135	jt_eaton
453	131	jt_eaton
454	135	jt_eaton
455	131	jt_eaton
456
457
458	135	jt_eaton