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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [io/] [ip/] [io_timer/] [sim/] [testbenches/] [xml/] [io_timer_def_tb.xml] - Blame information for rev 131

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xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
 
opencores.org
io
io_timer
def_tb
 
 
 
 
 
 

 
 
 
 

  gen_verilog
  104.0
  none
  common
  ./tools/verilog/gen_verilog
    
    
      destination
      top.tb
    
    
      dest_dir
      ../verilog
    
    
      top
    
  

 
 

 
 
 
 
 


    BUS_ADDR_WIDTH4

 
 
       
 
              
              Params
              
              
                                   spirit:library="io"
                                   spirit:name="io_timer"
                                   spirit:version="def_dut.params"/>
              
              
 
 
 
              
              Bfm
              
                                   spirit:library="io"
                                   spirit:name="io_timer"
                                   spirit:version="bfm.design"/>
              
 
 
 
              
              icarus
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="icarus"/>
              
              
 
              
              headers
              Verilog
              
              
 
 
              
              commoncommon
              Verilog
              
                     
                            fs-common
                     
              
 
 
 
              
              sim:*Simulation:*
              Verilog
              
                     
                            fs-sim
                     
              
 
 
              
              lint:*Lint:*
              Verilog
              
                     
                            fs-lint
                     
              
 
      
 
 
 
 
 

 
 
 
 
 
  
 
 
    
      fs-common
 
      
        
        ../verilog/top.ext
        verilogSourcefragment
      
 
 
 
    
 
 
    
      fs-sim
 
      
        
        ../verilog/common/top.tb
        verilogSourcemodule
      
 
 
 
    
 
 
    
      fs-lint
 
      
        
        ../verilog/common/top.tb
        verilogSourcemodule
      
 
 
 
    
 
 
 
 
 
  
 
 
 
 


Line No.	Rev	Author	Line
1	131	jt_eaton
2
30
31			`xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"`
32			`xmlns:socgen="http://opencores.org"`
33			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
34			`xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009`
35			`http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">`
36
37			`opencores.org`
38			`io`
39			`io_timer`
40			`def_tb`
41
42
43
44
45
46
47
48
49
50
51
52
53			`gen_verilog`
54			`104.0`
55			`none`
56			`common`
57			`./tools/verilog/gen_verilog`
58
59
60			`destination`
61			`top.tb`
62
63
64			`dest_dir`
65			`../verilog`
66
67
68			`top`
69
70
71
72
73
74
75
76
77
78
79
80
81
82			`BUS_ADDR_WIDTH4`
83
84
85
86
87
88
89			`Params`
90
91
92			`spirit:library="io"`
93			`spirit:name="io_timer"`
94			`spirit:version="def_dut.params"/>`
95
96
97
98
99
100
101			`Bfm`
102
103			`spirit:library="io"`
104			`spirit:name="io_timer"`
105			`spirit:version="bfm.design"/>`
106
107
108
109
110
111			`icarus`
112
113
114			`spirit:library="Testbench"`
115			`spirit:name="toolflow"`
116			`spirit:version="icarus"/>`
117
118
119
120
121			`headers`
122			`Verilog`
123
124
125
126
127
128			`commoncommon`
129			`Verilog`
130
131
132			`fs-common`
133
134
135
136
137
138
139			`sim:Simulation:`
140			`Verilog`
141
142
143			`fs-sim`
144
145
146
147
148
149			`lint:Lint:`
150			`Verilog`
151
152
153			`fs-lint`
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173			`fs-common`
174
175
176
177			`../verilog/top.ext`
178			`verilogSourcefragment`
179
180
181
182
183
184
185
186
187			`fs-sim`
188
189
190
191			`../verilog/common/top.tb`
192			`verilogSourcemodule`
193
194
195
196
197
198
199
200
201			`fs-lint`
202
203
204
205			`../verilog/common/top.tb`
206			`verilogSourcemodule`
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222

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Subversion Repositories socgen

[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [io/] [ip/] [io_timer/] [sim/] [testbenches/] [xml/] [io_timer_def_tb.xml] - Blame information for rev 131