OpenCores
URL https://opencores.org/ocsvn/socgen/socgen/trunk

Subversion Repositories socgen

[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [io/] [ip/] [io_utimer/] [doc/] [mem_map.txt] - Blame information for rev 131

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 131 jt_eaton
 
2
io_module
3
 
4
                 GPIO_0_IN      = 8000;
5
                 GPIO_0_OE      = 8001;
6
                 GPIO_0_OUT     = 8002;
7
 
8
                 GPIO_1_IN      = 8004;
9
                 GPIO_1_OE      = 8005;
10
                 GPIO_1_OUT     = 8006;
11
 
12
                 TIMER_0_START  = 8010;    TIMER_START:     rdata  = {4'h0,irq,trig,run,idle};
13
                 TIMER_0_COUNT  = 8011;
14
                 TIMER_0_END    = 8012;
15
 
16
                 TIMER_1_START  = 8020;    TIMER_START:     rdata  = {4'h0,irq,trig,run,idle};
17
                 TIMER_1_COUNT  = 8021;
18
                 TIMER_1_END    = 8022;
19
 
20
 
21
 
22
                 XMIT_DATA     =  8030;
23
                 RCV_DATA      =  8031;
24
                 CNTRL         =  8032;   // TX_IRQ_EN,RX_IRQ_EN,0,0,RTS,TX_BREAK,FORCE_PARITY,PARITY
25
                 STATUS        =  8033;    {status[7:1],rx_data_avail};
26
 
27
                 INT_IN         = 8040;  {ext_in[3:0],tx_irq,rx_irq,tim_1_irq,tim_0_irq}),
28
 
29
 
30
                 IRQ_ENABLE     = 8041;
31
                 NMI_ENABLE     = 8042;
32
                 IRQ_ACT        = 8043;
33
                 NMI_ACT        = 8044;
34
 
35
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.