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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [io/] [ip/] [io_vic/] [rtl/] [xml/] [io_vic_def.xml] - Blame information for rev 131

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xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
 
opencores.org
io
io_vic
def  default
 
 
 

 
 slave_clk
  
  
  
    
      
        clk
        clk
      
    
 
 
 
 slave_reset
  
  
  
    
      
        reset
        reset
      
    
 
 
 
mb
   
   
   little
   8
     
     
        
         rdata
         
         rdata
           wire
           70
         
       
 
        
         addr
         
         addr
           30
         
       
 
        
         wdata
         
         wdata
           70
         
       
 
 
        
         rd
         
         rd
         
       
 
        
         wr
         
         wr
         
       
 
        
         cs
         
         cs
         
       
 
      
  
 
 

 
 

 
 
 
 
 
 
 

  gen_registers
  103.0
  common
  none
  ./tools/regtool/gen_registers
    
    
      bus_intf
      mb
    
    
      dest_dir
      ../verilog
    
  

 
 

  gen_verilog
  104.0
  none
  common
  ./tools/verilog/gen_verilog
  
    
      destination
      top
    
    
      dest_dir
      ../verilog
    
  

 
 
 
 
 

 
 
 
  
 
    
      fs-common
 
      
        
        ../verilog/top.body
        verilogSourcefragment
      
 
 
    
 
 
    
      fs-sim
 
      
        
        ../verilog/copyright.v
        verilogSourceinclude
      
 
      
        
        ../verilog/common/top
        verilogSourcemodule
      
 
 
    
        mb
        ../verilog/io_vic_def_mb
        verilogSourcemodule
      
 
 
 
    
 
 
 
 
 
  
 
 
 
 
 

       
 
              
              Hierarchical
 
              
                                   spirit:library="io"
                                   spirit:name="io_vic"
                                   spirit:version="def.design"/>
              
 
 
              
              verilog
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="verilog"/>
              
              
 
 
 
 
 
              
              commoncommon
 
              Verilog
              
                     
                            fs-common
                     
              
 
              
              sim:*Simulation:*
 
              Verilog
              
                     
                            fs-sim
                     
              
 
              
              syn:*Synthesis:*
 
              Verilog
              
                     
                            fs-sim
                     
              
 
 
 
              
              doc
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="documentation"/>
              
              :*Documentation:*
              Verilog
              
 
 
 
      
 
 

IRQ_MODE8'h00
VEC_008'he0
VEC_018'he2
VEC_028'he4
VEC_038'he6
VEC_048'he8
VEC_058'hea
VEC_068'hec
VEC_078'hee
VEC_NONE8'h00

 
 

 
 
enable
wire
in

 
 
int_in
wire
in
70

 
irq_out
reg
out

 
vector
reg
out
70

 


 
 
 


 mb
8

 mb
 0x00
 
  
  mb_microbus
  0x10
  8
 
 
 
   int_in
   0x0
   8
   read-only
  
 
 
   irq_enable
   0x2
   8
   read-write
  
 
 
 
   irq_act
   0x6
   8
   read-only
  
 
 
   irq_vec
   0x8
   8
   read-only
  
 
 
  
 
 

 

 
 
 
 
 
 


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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [io/] [ip/] [io_vic/] [rtl/] [xml/] [io_vic_def.xml] - Blame information for rev 131

Line No.	Rev	Author	Line
1	131	jt_eaton
2
30
31			`xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"`
32			`xmlns:socgen="http://opencores.org"`
33			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
34			`xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009`
35			`http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">`
36
37			`opencores.org`
38			`io`
39			`io_vic`
40			`def default`
41
42
43
44
45
46			`slave_clk`
47
48
49
50
51
52			`clk`
53			`clk`
54
55
56
57
58
59			`slave_reset`
60
61
62
63
64
65			`reset`
66			`reset`
67
68
69
70
71
72			`mb`
73
74
75			`little`
76			`8`
77
78
79
80			`rdata`
81
82			`rdata`
83			`wire`
84			`70`
85
86
87
88
89			`addr`
90
91			`addr`
92			`30`
93
94
95
96
97			`wdata`
98
99			`wdata`
100			`70`
101
102
103
104
105
106			`rd`
107
108			`rd`
109
110
111
112
113			`wr`
114
115			`wr`
116
117
118
119
120			`cs`
121
122			`cs`
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142			`gen_registers`
143			`103.0`
144			`common`
145			`none`
146			`./tools/regtool/gen_registers`
147
148
149			`bus_intf`
150			`mb`
151
152
153			`dest_dir`
154			`../verilog`
155
156
157
158
159
160
161			`gen_verilog`
162			`104.0`
163			`none`
164			`common`
165			`./tools/verilog/gen_verilog`
166
167
168			`destination`
169			`top`
170
171
172			`dest_dir`
173			`../verilog`
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189			`fs-common`
190
191
192
193			`../verilog/top.body`
194			`verilogSourcefragment`
195
196
197
198
199
200
201
202			`fs-sim`
203
204
205
206			`../verilog/copyright.v`
207			`verilogSourceinclude`
208
209
210
211
212			`../verilog/common/top`
213			`verilogSourcemodule`
214
215
216
217
218			`mb`
219			`../verilog/io_vic_def_mb`
220			`verilogSourcemodule`
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241			`Hierarchical`
242
243
244			`spirit:library="io"`
245			`spirit:name="io_vic"`
246			`spirit:version="def.design"/>`
247
248
249
250
251			`verilog`
252
253
254			`spirit:library="Testbench"`
255			`spirit:name="toolflow"`
256			`spirit:version="verilog"/>`
257
258
259
260
261
262
263
264
265			`commoncommon`
266
267			`Verilog`
268
269
270			`fs-common`
271
272
273
274
275			`sim:Simulation:`
276
277			`Verilog`
278
279
280			`fs-sim`
281
282
283
284
285			`syn:Synthesis:`
286
287			`Verilog`
288
289
290			`fs-sim`
291
292
293
294
295
296
297			`doc`
298
299
300			`spirit:library="Testbench"`
301			`spirit:name="toolflow"`
302			`spirit:version="documentation"/>`
303
304			`:Documentation:`
305			`Verilog`
306
307
308
309
310
311
312
313
314			`IRQ_MODE8'h00`
315			`VEC_008'he0`
316			`VEC_018'he2`
317			`VEC_028'he4`
318			`VEC_038'he6`
319			`VEC_048'he8`
320			`VEC_058'hea`
321			`VEC_068'hec`
322			`VEC_078'hee`
323			`VEC_NONE8'h00`
324
325
326
327
328
329
330			`enable`
331			`wire`
332			`in`
333
334
335
336			`int_in`
337			`wire`
338			`in`
339			`70`
340
341
342			`irq_out`
343			`reg`
344			`out`
345
346
347			`vector`
348			`reg`
349			`out`
350			`70`
351
352
353
354
355
356
357
358
359
360			`mb`
361			`8`
362
363			`mb`
364			`0x00`
365
366
367			`mb_microbus`
368			`0x10`
369			`8`
370
371
372
373			`int_in`
374			`0x0`
375			`8`
376			`read-only`
377
378
379
380			`irq_enable`
381			`0x2`
382			`8`
383			`read-write`
384
385
386
387
388			`irq_act`
389			`0x6`
390			`8`
391			`read-only`
392
393
394
395			`irq_vec`
396			`0x8`
397			`8`
398			`read-only`
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414