URL https://opencores.org/ocsvn/socgen/socgen/trunk

Subversion Repositories socgen

[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [io/] [ip/] [io_vic/] [rtl/] [xml/] [io_vic_def.xml] - Blame information for rev 133

Go to most recent revision | Details | Compare with Previous | View Log





xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
 
opencores.org
io
io_vic
def  default
 
 
 

 
 slave_clk
  
  
  
    
      
        clk
        clk
      
    
 
 
 
 slave_reset
  
  
  
    
      
        reset
        reset
      
    
 
 
 
mb
   
   
   little
   8
     
     
        
         rdata
         
         rdata
           wire
           70
         
       
 
        
         addr
         
         addr
           30
         
       
 
        
         wdata
         
         wdata
           70
         
       
 
 
        
         rd
         
         rd
         
       
 
        
         wr
         
         wr
         
       
 
        
         cs
         
         cs
         
       
 
      
  
 
 

 
 

 
 
 
 

  elab_verilog
  102.1
  none
  :*Simulation:*
  ./tools/verilog/elab_verilog
    
    
      dest_dir
      io_ports
    
  

 
 
 
 
 
 

  gen_registers
  102.1
  common
  none
  ./tools/regtool/gen_registers
    
    
      bus_intf
      mb
    
    
      dest_dir
      ../verilog
    
  

 
 

  gen_verilog
  104.0
  none
  common
  ./tools/verilog/gen_verilog
  
    
      destination
      top
    
    
      dest_dir
      ../verilog
    
  

 
 
 
 
 

 
 
 
  
 
    
      fs-common
 
      
        
        ../verilog/top.body
        verilogSourcefragment
      
 
 
    
 
 
    
      fs-sim
 
      
        
        ../verilog/copyright.v
        verilogSourceinclude
      
 
      
        
        ../verilog/common/top
        verilogSourcemodule
      
 
 
    
        mb
        ../verilog/io_vic_def_mb
        verilogSourcemodule
      
 
 
 
    
 
 
 
 
 
  
 
 
 
 
 

       
 
              
              Hierarchical
 
              
                                   spirit:library="io"
                                   spirit:name="io_vic"
                                   spirit:version="def.design"/>
              
 
 
              
              verilog
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="verilog"/>
              
              
 
 
 
 
 
              
              commoncommon
 
              Verilog
              
                     
                            fs-common
                     
              
 
              
              sim:*Simulation:*
 
              Verilog
              
                     
                            fs-sim
                     
              
 
              
              syn:*Synthesis:*
 
              Verilog
              
                     
                            fs-sim
                     
              
 
 
 
              
              doc
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="documentation"/>
              
              :*Documentation:*
              Verilog
              
 
 
 
      
 
 

IRQ_MODE8'h00
VEC_008'he0
VEC_018'he2
VEC_028'he4
VEC_038'he6
VEC_048'he8
VEC_058'hea
VEC_068'hec
VEC_078'hee
VEC_NONE8'h00

 
 

 
 
enable
wire
in

 
 
int_in
wire
in
70

 
irq_out
reg
out

 
vector
reg
out
70

 


 
 
 


 mb
8

 mb
 0x00
 
  
  mb_microbus
  0x10
  8
 
 
 
   int_in
   0x0
   8
   read-only
  
 
 
   irq_enable
   0x2
   8
   read-write
  
 
 
 
   irq_act
   0x6
   8
   read-only
  
 
 
   irq_vec
   0x8
   8
   read-only
  
 
 
  
 
 

 

 
 
 
 
 
 


Browse

Tools

Subversion Repositories socgen

[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [io/] [ip/] [io_vic/] [rtl/] [xml/] [io_vic_def.xml] - Blame information for rev 133

Line No.	Rev	Author	Line
1	131	jt_eaton
2
30
31			`xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"`
32			`xmlns:socgen="http://opencores.org"`
33			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
34			`xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009`
35			`http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">`
36
37			`opencores.org`
38			`io`
39			`io_vic`
40			`def default`
41
42
43
44
45
46			`slave_clk`
47
48
49
50
51
52			`clk`
53			`clk`
54
55
56
57
58
59			`slave_reset`
60
61
62
63
64
65			`reset`
66			`reset`
67
68
69
70
71
72			`mb`
73
74
75			`little`
76			`8`
77
78
79
80			`rdata`
81
82			`rdata`
83			`wire`
84			`70`
85
86
87
88
89			`addr`
90
91			`addr`
92			`30`
93
94
95
96
97			`wdata`
98
99			`wdata`
100			`70`
101
102
103
104
105
106			`rd`
107
108			`rd`
109
110
111
112
113			`wr`
114
115			`wr`
116
117
118
119
120			`cs`
121
122			`cs`
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138	133	jt_eaton
139			`elab_verilog`
140			`102.1`
141			`none`
142			`:Simulation:`
143			`./tools/verilog/elab_verilog`
144
145
146			`dest_dir`
147			`io_ports`
148
149
150
151	131	jt_eaton
152
153
154	133	jt_eaton
155
156
157	131	jt_eaton
158			`gen_registers`
159	133	jt_eaton	`102.1`
160	131	jt_eaton	`common`
161			`none`
162			`./tools/regtool/gen_registers`
163
164
165			`bus_intf`
166			`mb`
167
168
169			`dest_dir`
170			`../verilog`
171
172
173
174
175
176
177			`gen_verilog`
178			`104.0`
179			`none`
180			`common`
181			`./tools/verilog/gen_verilog`
182
183
184			`destination`
185			`top`
186
187
188			`dest_dir`
189			`../verilog`
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205			`fs-common`
206
207
208
209			`../verilog/top.body`
210			`verilogSourcefragment`
211
212
213
214
215
216
217
218			`fs-sim`
219
220
221
222			`../verilog/copyright.v`
223			`verilogSourceinclude`
224
225
226
227
228			`../verilog/common/top`
229			`verilogSourcemodule`
230
231
232
233
234			`mb`
235			`../verilog/io_vic_def_mb`
236			`verilogSourcemodule`
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257			`Hierarchical`
258
259
260			`spirit:library="io"`
261			`spirit:name="io_vic"`
262			`spirit:version="def.design"/>`
263
264
265
266
267			`verilog`
268
269
270			`spirit:library="Testbench"`
271			`spirit:name="toolflow"`
272			`spirit:version="verilog"/>`
273
274
275
276
277
278
279
280
281			`commoncommon`
282
283			`Verilog`
284
285
286			`fs-common`
287
288
289
290
291			`sim:Simulation:`
292
293			`Verilog`
294
295
296			`fs-sim`
297
298
299
300
301			`syn:Synthesis:`
302
303			`Verilog`
304
305
306			`fs-sim`
307
308
309
310
311
312
313			`doc`
314
315
316			`spirit:library="Testbench"`
317			`spirit:name="toolflow"`
318			`spirit:version="documentation"/>`
319
320			`:Documentation:`
321			`Verilog`
322
323
324
325
326
327
328
329
330			`IRQ_MODE8'h00`
331			`VEC_008'he0`
332			`VEC_018'he2`
333			`VEC_028'he4`
334			`VEC_038'he6`
335			`VEC_048'he8`
336			`VEC_058'hea`
337			`VEC_068'hec`
338			`VEC_078'hee`
339			`VEC_NONE8'h00`
340
341
342
343
344
345
346			`enable`
347			`wire`
348			`in`
349
350
351
352			`int_in`
353			`wire`
354			`in`
355			`70`
356
357
358			`irq_out`
359			`reg`
360			`out`
361
362
363			`vector`
364			`reg`
365			`out`
366			`70`
367
368
369
370
371
372
373
374
375
376			`mb`
377			`8`
378
379			`mb`
380			`0x00`
381
382
383			`mb_microbus`
384			`0x10`
385			`8`
386
387
388
389			`int_in`
390			`0x0`
391			`8`
392			`read-only`
393
394
395
396			`irq_enable`
397			`0x2`
398			`8`
399			`read-write`
400
401
402
403
404			`irq_act`
405			`0x6`
406			`8`
407			`read-only`
408
409
410
411			`irq_vec`
412			`0x8`
413			`8`
414			`read-only`
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430