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jt_eaton |
/**********************************************************************/
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/* */
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/* ------- */
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/* / SOC \ */
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/* / GEN \ */
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/* / COMPONENT \ */
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/* ============== */
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/* | | */
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/* |____________| */
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/* */
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/* */
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/* Author(s): */
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/* - John Eaton, jt_eaton@opencores.org */
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/* */
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/**********************************************************************/
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/* */
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/* Copyright (C) <2010> */
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/* */
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/* This source file may be used and distributed without */
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/* restriction provided that this copyright statement is not */
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/* removed from the file and that any derivative work contains */
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/* the original copyright notice and the associated disclaimer. */
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/* */
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/* This source file is free software; you can redistribute it */
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/* and/or modify it under the terms of the GNU Lesser General */
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/* Public License as published by the Free Software Foundation; */
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/* either version 2.1 of the License, or (at your option) any */
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/* later version. */
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/* */
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/* This source is distributed in the hope that it will be */
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/* useful, but WITHOUT ANY WARRANTY; without even the implied */
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/* warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR */
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/* PURPOSE. See the GNU Lesser General Public License for more */
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/* details. */
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/* */
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/* You should have received a copy of the GNU Lesser General */
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/* Public License along with this source; if not, download it */
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/* from http://www.opencores.org/lgpl.shtml */
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/* */
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/**********************************************************************/
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// display io controller for digilent Basys fpga board
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reg [3:0] divide;
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reg [3:0] number;
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wire one_usec;
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always@(posedge clk ) led_pad_out <= PosL;
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always@(posedge clk ) PosS <= sw_pad_in;
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always@(posedge clk ) PosB <= btn_pad_in;
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cde_divider_def
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#(.SIZE(6))
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cde_divider(
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.clk (clk),
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.reset (reset),
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.enable (1'b1),
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.divider_in (6'b100000),
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.divider_out (one_usec)
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);
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always@(posedge clk)
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if(reset) divide <= 4'b0000;
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else
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if(one_usec) divide <= divide+4'b0001;
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else divide <= divide;
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always@(posedge clk) dp_pad_out <= 1'b1;
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always@(posedge clk)
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if(reset) an_pad_out <= 4'b1111;
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else
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if(divide[3:0] == 4'b0010) an_pad_out <= 4'b1110;
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else
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if(divide[3:0] == 4'b0110) an_pad_out <= 4'b1101;
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else
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if(divide[3:0] == 4'b1010) an_pad_out <= 4'b1011;
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else
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if(divide[3:0] == 4'b1110) an_pad_out <= 4'b0111;
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else an_pad_out <= 4'b1111;
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always@(posedge clk)
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if(divide[3:2] == 2'b00) number <= PosD[3:0];
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else
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if(divide[3:2] == 2'b01) number <= PosD[7:4];
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else
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if(divide[3:2] == 2'b10) number <= PosD[11:8];
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else
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if(divide[3:2] == 2'b11) number <= PosD[15:12];
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else number <= number;
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always@(posedge clk)
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if(reset) seg_pad_out <= 7'b1111111;
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else
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if(number[3:0] == 4'b0000) seg_pad_out <= 7'b1000000;
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else
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if(number[3:0] == 4'b0001) seg_pad_out <= 7'b1111001;
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else
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if(number[3:0] == 4'b0010) seg_pad_out <= 7'b0100100;
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else
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if(number[3:0] == 4'b0011) seg_pad_out <= 7'b0110000;
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else
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if(number[3:0] == 4'b0100) seg_pad_out <= 7'b0011001;
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else
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if(number[3:0] == 4'b0101) seg_pad_out <= 7'b0010010;
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else
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if(number[3:0] == 4'b0110) seg_pad_out <= 7'b0000010;
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else
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if(number[3:0] == 4'b0111) seg_pad_out <= 7'b1111000;
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else
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if(number[3:0] == 4'b1000) seg_pad_out <= 7'b0000000;
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else
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if(number[3:0] == 4'b1001) seg_pad_out <= 7'b0011000;
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else
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if(number[3:0] == 4'b1010) seg_pad_out <= 7'b0001000;
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else
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if(number[3:0] == 4'b1011) seg_pad_out <= 7'b0000011;
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else
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if(number[3:0] == 4'b1100) seg_pad_out <= 7'b1000110;
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else
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if(number[3:0] == 4'b1101) seg_pad_out <= 7'b0100001;
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else
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if(number[3:0] == 4'b1110) seg_pad_out <= 7'b0000110;
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else
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if(number[3:0] == 4'b1111) seg_pad_out <= 7'b0001110;
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else seg_pad_out <= 7'b1111111;
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