OpenCores
URL https://opencores.org/ocsvn/socgen/socgen/trunk

Subversion Repositories socgen

[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [logic/] [ip/] [disp_io/] [rtl/] [verilog/] [top.jtag] - Blame information for rev 133

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 133 jt_eaton
 
2
 
3
 
4
 
5
 
6
 
7
 
8
 
9
 
10
 
11
 
12
 
13
 
14
reg  [3:0]          divide;
15
reg  [3:0]          number;
16
 
17
 
18
 
19
 
20
always@(posedge clk )  led_pad_out <= PosL | update_value;
21
always@(posedge clk )  PosS        <= sw_pad_in;
22
always@(posedge clk )  PosB        <= btn_pad_in;
23
 
24
 
25
 
26
 
27
always@(posedge clk)
28
  if(reset)      divide <= 4'b0000;
29
  else
30
  if(one_usec)   divide <= divide+4'b0001;
31
  else           divide <= divide;
32
 
33
always@(posedge clk)   dp_pad_out   <= 1'b1;
34
 
35
 
36
 
37
always@(posedge clk)
38
  if(reset)                   an_pad_out <= 4'b1111;
39
  else
40
  if(divide[3:0] == 4'b0010)  an_pad_out <= 4'b1110;
41
  else
42
  if(divide[3:0] == 4'b0110)  an_pad_out <= 4'b1101;
43
  else
44
  if(divide[3:0] == 4'b1010)  an_pad_out <= 4'b1011;
45
  else
46
  if(divide[3:0] == 4'b1110)  an_pad_out <= 4'b0111;
47
  else                        an_pad_out <= 4'b1111;
48
 
49
 
50
 
51
always@(posedge clk)
52
  if(divide[3:2] == 2'b00)  number <= PosD[3:0];
53
  else
54
  if(divide[3:2] == 2'b01)  number <= PosD[7:4];
55
  else
56
  if(divide[3:2] == 2'b10)  number <= PosD[11:8];
57
  else
58
  if(divide[3:2] == 2'b11)  number <= PosD[15:12];
59
  else                      number <= number;
60
 
61
 
62
 
63
always@(posedge clk)
64
  if(reset)                   seg_pad_out <= 7'b1111111;
65
  else
66
  if(number[3:0] == 4'b0000)  seg_pad_out <= 7'b1000000;
67
  else
68
  if(number[3:0] == 4'b0001)  seg_pad_out <= 7'b1111001;
69
  else
70
  if(number[3:0] == 4'b0010)  seg_pad_out <= 7'b0100100;
71
  else
72
  if(number[3:0] == 4'b0011)  seg_pad_out <= 7'b0110000;
73
  else
74
  if(number[3:0] == 4'b0100)  seg_pad_out <= 7'b0011001;
75
  else
76
  if(number[3:0] == 4'b0101)  seg_pad_out <= 7'b0010010;
77
  else
78
  if(number[3:0] == 4'b0110)  seg_pad_out <= 7'b0000010;
79
  else
80
  if(number[3:0] == 4'b0111)  seg_pad_out <= 7'b1111000;
81
  else
82
  if(number[3:0] == 4'b1000)  seg_pad_out <= 7'b0000000;
83
  else
84
  if(number[3:0] == 4'b1001)  seg_pad_out <= 7'b0011000;
85
  else
86
  if(number[3:0] == 4'b1010)  seg_pad_out <= 7'b0001000;
87
  else
88
  if(number[3:0] == 4'b1011)  seg_pad_out <= 7'b0000011;
89
  else
90
  if(number[3:0] == 4'b1100)  seg_pad_out <= 7'b1000110;
91
  else
92
  if(number[3:0] == 4'b1101)  seg_pad_out <= 7'b0100001;
93
  else
94
  if(number[3:0] == 4'b1110)  seg_pad_out <= 7'b0000110;
95
  else
96
  if(number[3:0] == 4'b1111)  seg_pad_out <= 7'b0001110;
97
  else                        seg_pad_out <= 7'b1111111;
98
 
99
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.