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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [logic/] [ip/] [disp_io/] [sim/] [icarus/] [jtag/] [test_define] - Blame information for rev 133

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reg actual;
 
 
parameter       EXTEST=4'b0000;
parameter       SAMPLE=4'b0001;
parameter       HIGHZ_MODE=4'b0010;
parameter       CHIP_ID_ACCESS=4'b0011;
parameter       CLAMP=4'b1000;
parameter       RPC_DATA=4'b1010;
parameter       RPC_ADD=4'b1001;
parameter       BYPASS=4'b1111;
parameter       INST_RETURN=4'b1101;
 
 
 
initial
 begin
 $display("              ");
 $display("          ===================================================");
 $display("%t  Test Start",$realtime);
 $display("          ===================================================");
 $display("              ");
 test.R_PosD           = 16'b0000000000000000;
 test.R_PosL           = 8'b00000000;
 test.R_sw_pad_in      = 8'b00000000;
 test.R_btn_pad_in     = 4'b0000;
 
 test.cg.next(8);
 
 
 
 
 
test.cg.next(2);
test.jtag_model.enable_tclk;
test.cg.next(20);
 
test.cg.next(20);
test.jtag_model.enable_trst_n;
test.jtag_model.enable_reset;
test.jtag_model.init;
test.cg.next(10);
test.jtag_model.LoadTapInst(EXTEST,INST_RETURN);
test.cg.next(100);
test.jtag_model.LoadTapInst(CLAMP,INST_RETURN);
 
 
test.cg.next(100);
test.jtag_model.LoadTapInst(CHIP_ID_ACCESS,INST_RETURN);
test.jtag_model.Shift_Cmp_32(32'ha5a5a5a5,32'h12345678);
 
 
test.cg.next(100);
test.jtag_model.LoadTapInst(RPC_ADD,INST_RETURN);
                Shift_Cmp_8(8'h00,8'h00);
test.R_sw_pad_in      = 8'h34;
test.cg.next(100);
                Shift_Cmp_8(8'h34,8'h34);
test.R_sw_pad_in      = 8'h56;
test.cg.next(100);
                Shift_Cmp_8(8'h56,8'h56);
test.R_sw_pad_in      = 8'h12;
test.cg.next(100);
                Shift_Cmp_8(8'hff,8'h12);
test.R_sw_pad_in      = 8'hff;
test.cg.next(100);
                Shift_Cmp_8(8'hcd,8'hff);
 
 
test.cg.next(100);
 
 
 
 
 
test.jtag_model.LoadTapInst(BYPASS,INST_RETURN);
 
 
Shift_Cmp_8(8'h12,8'h24);
 
test.cg.next(100);
 
 
test.cg.exit;
end
 
 
 
 
 
 
task automatic  Shift_Cmp_8;    // Initialize boundary register with outputs disabled
                         // This tasks starts at RT_IDLE and ends at SHIFT_DR
 
  parameter [15:0] LENGTH =  8;
 
 
  input [LENGTH:1]  Dataout;
  input [LENGTH:1]  DataExp;
 
  integer i;
 
  reg [LENGTH:1]  DataBack;
 
  begin
    test.jtag_model.Clk_bit(1'b1,1'b0,actual);// Transition from RT_IDLE to SELECT_DR
    test.jtag_model.Clk_bit(1'b0,1'b0,actual);// Transition from SELECT_DR to CAPTURE_DR
    test.jtag_model.Clk_bit(1'b0,1'b0,actual);// Transition from CAPTURE_DR to SHIFT_DR
    for (i = 1; i <= LENGTH; i = i+1)
       test.jtag_model.Clk_bit((i==LENGTH),Dataout[i],DataBack[i]);
    $display  ("%t  %m    Shift_data_register    wr-%h  exp-%h rd-%h    ",$realtime,Dataout,DataExp,DataBack  );
 
   if (DataBack  !== DataExp )
   begin
   test.cg.fail  (" Shift_cmp  receive error  ");
   end
 
    test.jtag_model.Clk_bit(1'b1,1'b0,actual);//Transition from EXIT1-DR to UPDATE-DR
    test.jtag_model.Clk_bit(1'b0,1'b0,actual);// Transition from UPDATE-DR to IDLE
  end
endtask // ShiftRegister
 
 
 
 
task automatic  Shift_Cmp_24;    // Initialize boundary register with outputs disabled
                         // This tasks starts at RT_IDLE and ends at SHIFT_DR
 
  parameter [15:0] LENGTH =  24;
 
 
  input [LENGTH:1]  Dataout;
  input [LENGTH:1]  DataExp;
 
  integer i;
 
  reg [LENGTH:1]  DataBack;
 
  begin
    test.jtag_model.Clk_bit(1'b1,1'b0,actual);// Transition from RT_IDLE to SELECT_DR
    test.jtag_model.Clk_bit(1'b0,1'b0,actual);// Transition from SELECT_DR to CAPTURE_DR
    test.jtag_model.Clk_bit(1'b0,1'b0,actual);// Transition from CAPTURE_DR to SHIFT_DR
    for (i = 1; i <= LENGTH; i = i+1)
       test.jtag_model.Clk_bit((i==LENGTH),Dataout[i],DataBack[i]);
    $display  ("%t  %m    Shift_data_register    wr-%h  exp-%h rd-%h    ",$realtime,Dataout,DataExp,DataBack  );
 
   if (DataBack  !== DataExp )
   begin
   test.cg.fail  (" Shift_cmp  receive error  ");
   end
 
    test.jtag_model.Clk_bit(1'b1,1'b0,actual);//Transition from EXIT1-DR to UPDATE-DR
    test.jtag_model.Clk_bit(1'b0,1'b0,actual);// Transition from UPDATE-DR to IDLE
  end
endtask // ShiftRegister
 
 
 
 
 
 
 

Line No.	Rev	Author	Line
1	133	jt_eaton
2			`reg actual;`
3
4
5			`parameter EXTEST=4'b0000;`
6			`parameter SAMPLE=4'b0001;`
7			`parameter HIGHZ_MODE=4'b0010;`
8			`parameter CHIP_ID_ACCESS=4'b0011;`
9			`parameter CLAMP=4'b1000;`
10			`parameter RPC_DATA=4'b1010;`
11			`parameter RPC_ADD=4'b1001;`
12			`parameter BYPASS=4'b1111;`
13			`parameter INST_RETURN=4'b1101;`
14
15
16
17			`initial`
18			`begin`
19			`$display(" ");`
20			`$display(" ===================================================");`
21			`$display("%t Test Start",$realtime);`
22			`$display(" ===================================================");`
23			`$display(" ");`
24			`test.R_PosD = 16'b0000000000000000;`
25			`test.R_PosL = 8'b00000000;`
26			`test.R_sw_pad_in = 8'b00000000;`
27			`test.R_btn_pad_in = 4'b0000;`
28
29			`test.cg.next(8);`
30
31
32
33
34
35			`test.cg.next(2);`
36			`test.jtag_model.enable_tclk;`
37			`test.cg.next(20);`
38
39			`test.cg.next(20);`
40			`test.jtag_model.enable_trst_n;`
41			`test.jtag_model.enable_reset;`
42			`test.jtag_model.init;`
43			`test.cg.next(10);`
44			`test.jtag_model.LoadTapInst(EXTEST,INST_RETURN);`
45			`test.cg.next(100);`
46			`test.jtag_model.LoadTapInst(CLAMP,INST_RETURN);`
47
48
49			`test.cg.next(100);`
50			`test.jtag_model.LoadTapInst(CHIP_ID_ACCESS,INST_RETURN);`
51			`test.jtag_model.Shift_Cmp_32(32'ha5a5a5a5,32'h12345678);`
52
53
54			`test.cg.next(100);`
55			`test.jtag_model.LoadTapInst(RPC_ADD,INST_RETURN);`
56			`Shift_Cmp_8(8'h00,8'h00);`
57			`test.R_sw_pad_in = 8'h34;`
58			`test.cg.next(100);`
59			`Shift_Cmp_8(8'h34,8'h34);`
60			`test.R_sw_pad_in = 8'h56;`
61			`test.cg.next(100);`
62			`Shift_Cmp_8(8'h56,8'h56);`
63			`test.R_sw_pad_in = 8'h12;`
64			`test.cg.next(100);`
65			`Shift_Cmp_8(8'hff,8'h12);`
66			`test.R_sw_pad_in = 8'hff;`
67			`test.cg.next(100);`
68			`Shift_Cmp_8(8'hcd,8'hff);`
69
70
71			`test.cg.next(100);`
72
73
74
75
76
77			`test.jtag_model.LoadTapInst(BYPASS,INST_RETURN);`
78
79
80			`Shift_Cmp_8(8'h12,8'h24);`
81
82			`test.cg.next(100);`
83
84
85			`test.cg.exit;`
86			`end`
87
88
89
90
91
92
93			`task automatic Shift_Cmp_8; // Initialize boundary register with outputs disabled`
94			`// This tasks starts at RT_IDLE and ends at SHIFT_DR`
95
96			`parameter [15:0] LENGTH = 8;`
97
98
99			`input [LENGTH:1] Dataout;`
100			`input [LENGTH:1] DataExp;`
101
102			`integer i;`
103
104			`reg [LENGTH:1] DataBack;`
105
106			`begin`
107			`test.jtag_model.Clk_bit(1'b1,1'b0,actual);// Transition from RT_IDLE to SELECT_DR`
108			`test.jtag_model.Clk_bit(1'b0,1'b0,actual);// Transition from SELECT_DR to CAPTURE_DR`
109			`test.jtag_model.Clk_bit(1'b0,1'b0,actual);// Transition from CAPTURE_DR to SHIFT_DR`
110			`for (i = 1; i <= LENGTH; i = i+1)`
111			`test.jtag_model.Clk_bit((i==LENGTH),Dataout[i],DataBack[i]);`
112			`$display ("%t %m Shift_data_register wr-%h exp-%h rd-%h ",$realtime,Dataout,DataExp,DataBack );`
113
114			`if (DataBack !== DataExp )`
115			`begin`
116			`test.cg.fail (" Shift_cmp receive error ");`
117			`end`
118
119			`test.jtag_model.Clk_bit(1'b1,1'b0,actual);//Transition from EXIT1-DR to UPDATE-DR`
120			`test.jtag_model.Clk_bit(1'b0,1'b0,actual);// Transition from UPDATE-DR to IDLE`
121			`end`
122			`endtask // ShiftRegister`
123
124
125
126
127			`task automatic Shift_Cmp_24; // Initialize boundary register with outputs disabled`
128			`// This tasks starts at RT_IDLE and ends at SHIFT_DR`
129
130			`parameter [15:0] LENGTH = 24;`
131
132
133			`input [LENGTH:1] Dataout;`
134			`input [LENGTH:1] DataExp;`
135
136			`integer i;`
137
138			`reg [LENGTH:1] DataBack;`
139
140			`begin`
141			`test.jtag_model.Clk_bit(1'b1,1'b0,actual);// Transition from RT_IDLE to SELECT_DR`
142			`test.jtag_model.Clk_bit(1'b0,1'b0,actual);// Transition from SELECT_DR to CAPTURE_DR`
143			`test.jtag_model.Clk_bit(1'b0,1'b0,actual);// Transition from CAPTURE_DR to SHIFT_DR`
144			`for (i = 1; i <= LENGTH; i = i+1)`
145			`test.jtag_model.Clk_bit((i==LENGTH),Dataout[i],DataBack[i]);`
146			`$display ("%t %m Shift_data_register wr-%h exp-%h rd-%h ",$realtime,Dataout,DataExp,DataBack );`
147
148			`if (DataBack !== DataExp )`
149			`begin`
150			`test.cg.fail (" Shift_cmp receive error ");`
151			`end`
152
153			`test.jtag_model.Clk_bit(1'b1,1'b0,actual);//Transition from EXIT1-DR to UPDATE-DR`
154			`test.jtag_model.Clk_bit(1'b0,1'b0,actual);// Transition from UPDATE-DR to IDLE`
155			`end`
156			`endtask // ShiftRegister`
157
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Subversion Repositories socgen

[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [logic/] [ip/] [disp_io/] [sim/] [icarus/] [jtag/] [test_define] - Blame information for rev 133