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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [logic/] [ip/] [disp_io/] [sim/] [testbenches/] [verilog/] [tb.ext] - Blame information for rev 131

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reg   [3:0] R_btn_pad_in;
reg   [7:0] R_sw_pad_in;
reg  [15:0] R_PosD;
reg  [7:0]  R_PosL;
 
 
assign   btn_pad_in = R_btn_pad_in;
assign   sw_pad_in  = R_sw_pad_in;
assign   PosD       = R_PosD;
assign   PosL       = R_PosL;
 
 
assign STOP = 1'b0;
assign BAD = 1'b0;
 
 

Line No.	Rev	Author	Line
1	131	jt_eaton
2
3
4			`reg [3:0] R_btn_pad_in;`
5			`reg [7:0] R_sw_pad_in;`
6			`reg [15:0] R_PosD;`
7			`reg [7:0] R_PosL;`
8
9
10			`assign btn_pad_in = R_btn_pad_in;`
11			`assign sw_pad_in = R_sw_pad_in;`
12			`assign PosD = R_PosD;`
13			`assign PosL = R_PosL;`
14
15
16			`assign STOP = 1'b0;`
17			`assign BAD = 1'b0;`
18
19

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Subversion Repositories socgen

[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [logic/] [ip/] [disp_io/] [sim/] [testbenches/] [verilog/] [tb.ext] - Blame information for rev 131