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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [logic/] [ip/] [micro_bus/] [rtl/] [verilog/] [top.body.exp5] - Blame information for rev 131

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Line No. Rev Author Line
1 131 jt_eaton
 
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reg [7:0]  rdata_out_reg;
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always@(posedge clk)
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rdata_out_reg     <= mas_0_rdata_in  &
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                     mas_1_rdata_in  &
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                     mas_2_rdata_in  &
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                     mas_3_rdata_in  &
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                     mas_4_rdata_in;
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assign mas_0_rd_out    = rd_in;
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assign mas_1_rd_out    = rd_in;
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assign mas_2_rd_out    = rd_in;
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assign mas_3_rd_out    = rd_in;
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assign mas_4_rd_out    = rd_in;
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assign mas_0_wr_out    = wr_in;
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assign mas_1_wr_out    = wr_in;
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assign mas_2_wr_out    = wr_in;
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assign mas_3_wr_out    = wr_in;
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assign mas_4_wr_out    = wr_in;
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assign mas_0_wdata_out = wdata_in;
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assign mas_1_wdata_out = wdata_in;
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assign mas_2_wdata_out = wdata_in;
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assign mas_3_wdata_out = wdata_in;
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assign mas_4_wdata_out = wdata_in;
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assign mas_0_addr_out  = addr_in[7:0];
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assign mas_1_addr_out  = addr_in[7:0];
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assign mas_2_addr_out  = addr_in[7:0];
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assign mas_3_addr_out  = addr_in[7:0];
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assign mas_4_addr_out  = addr_in[7:0];
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assign  mas_0_cs_out = (addr_in[7:4] == 4'h0) && cs_in;
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assign  mas_1_cs_out = (addr_in[7:4] == 4'h1) && cs_in;
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assign  mas_2_cs_out = (addr_in[7:4] == 4'h2) && cs_in;
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assign  mas_3_cs_out = (addr_in[7:4] == 4'h3) && cs_in;
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assign  mas_4_cs_out = (addr_in[7:4] == 4'h4) && cs_in;
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assign   rdata_out = (rd_in && cs_in)?{8'h00,rdata_out_reg}:16'hffff;
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always@(posedge clk)
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if(reset || enable)
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   begin
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   wait_out  <= 1'b1;
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   end
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else
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    wait_out <= 1'b0;
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