Subversion Repositories socgen

reg [7:0]  rdata_out_reg;

always@(posedge clk)

rdata_out_reg     <= mas_0_rdata_in  &

                     mas_1_rdata_in  &

                     mas_2_rdata_in  &

                     mas_3_rdata_in  &

                     mas_4_rdata_in;

assign mas_0_rd_out    = rd_in;

assign mas_1_rd_out    = rd_in;

assign mas_2_rd_out    = rd_in;

assign mas_3_rd_out    = rd_in;

assign mas_4_rd_out    = rd_in;

assign mas_0_wr_out    = wr_in;

assign mas_1_wr_out    = wr_in;

assign mas_2_wr_out    = wr_in;

assign mas_3_wr_out    = wr_in;

assign mas_4_wr_out    = wr_in;

assign mas_0_wdata_out = wdata_in;

assign mas_1_wdata_out = wdata_in;

assign mas_2_wdata_out = wdata_in;

assign mas_3_wdata_out = wdata_in;

assign mas_4_wdata_out = wdata_in;

assign mas_0_addr_out  = addr_in[3:0];

assign mas_1_addr_out  = addr_in[3:0];

assign mas_2_addr_out  = addr_in[3:0];

assign mas_3_addr_out  = addr_in[3:0];

assign mas_4_addr_out  = addr_in[3:0];

assign  mas_0_cs_out = (addr_in[7:4] == 4'h0) && cs_in;

assign  mas_1_cs_out = (addr_in[7:4] == 4'h1) && cs_in;

assign  mas_2_cs_out = (addr_in[7:4] == 4'h2) && cs_in;

assign  mas_3_cs_out = (addr_in[7:4] == 4'h3) && cs_in;

assign  mas_4_cs_out = (addr_in[7:4] == 4'h4) && cs_in;

assign   rdata_out = (rd_in && cs_in)?{8'h00,rdata_out_reg}:16'hffff;

always@(posedge clk)

if(reset || enable)

   begin

   wait_out  <= 1'b1;

   end

else

    wait_out <= 1'b0;