URL https://opencores.org/ocsvn/socgen/socgen/trunk

Subversion Repositories socgen

[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [logic/] [ip/] [micro_bus/] [rtl/] [xml/] [micro_bus_def.xml] - Blame information for rev 133

Go to most recent revision | Details | Compare with Previous | View Log





xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
 
opencores.org
logic
micro_bus
def  default
 
 
 

 
 slave_clk
  
  
  
    
      
        clk
        clk
      
    
 
 
 
 slave_reset
  
  
  
    
      
        reset
        reset
      
    
 
 
 
 master_enable
  
  
  
    
      
        enable
        enable
      
    
 
 
 
 cpu
  
  
  
  
  
  
  
  
  
  
 
    
      
        addr
        addr_in
        150
        
      
      
        rdata
        rdata_out
        reg
        150
        
      
 
 
 
      
        wdata
        wdata_in
        70
        
      
 
 
      
        wr
        wr_in
        
      
 
 
      
        rd
        rd_in
        
      
 
 
 
    
 
 
 
 
 mem
  
  
   
 
 
    
 
      
        addr
        mem_addr
        150
        
      
 
      
        cs
        mem_cs
        reg
        
      
 
      
        wdata
        mem_wdata
        150
        
      
 
      
        rdata
        mem_rdata
        150
        
      
 
 
      
        wait
        mem_wait
        10
        
      
 
 
      
        rd
        mem_rd
        
      
 
      
        wr
        mem_wr
        
      
 
    
 
 
 
 
 
 
 data
  
  
 
           
 
    
 
      
        addr
        data_addr
        111
        
      
 
      
        cs
        data_cs
        reg
        
      
 
      
        wdata
        data_wdata
        150
        
      
 
      
        rdata
        data_rdata
        150
        
      
 
 
      
        be
        data_be
        10
        
      
 
 
      
        rd
        data_rd
        
      
 
      
        wr
        data_wr
        
      
 
    
 
 
 
 
 
 io_reg
  
  
 
           
 
    
 
      
        addr
        io_reg_addr
        70
        
      
 
      
        cs
        io_reg_cs
        reg
        
      
 
      
        wdata
        io_reg_wdata
        70
        
      
 
      
        rdata
        io_reg_rdata
        150
        
      
 
 
      
        wait
        io_reg_wait
        
      
 
 
      
        rd
        io_reg_rd
        
      
 
      
        wr
        io_reg_wr
        
      
 
    
 
 
 
 
 
 ext_mem
  
  
 
           
 
 
    
 
      
        addr
        ext_mem_addr
        130
        
      
 
      
        cs
        ext_mem_cs
        reg
        
      
 
      
        wdata
        ext_mem_wdata
        150
        
      
 
      
        rdata
        ext_mem_rdata
        150
        
      
 
 
      
        wait
        ext_mem_wait
        
      
 
 
      
        rd
        ext_mem_rd
        
      
 
      
        wr
        ext_mem_wr
        
      
 
    
 
 
 
 
 
 
 
 prog_rom_mem
  
  
 
 
  
    
 
      
        addr
        prog_rom_mem_addr
        110
        
      
 
      
        cs
        prog_rom_mem_cs
        reg
        
      
 
      
        wdata
        prog_rom_mem_wdata
        150
        
      
 
      
        rdata
        prog_rom_mem_rdata
        150
        
      
 
 
      
        rd
        prog_rom_mem_rd
        
      
 
      
        wr
        prog_rom_mem_wr
        
      
 
    
 
 
 
 
 
 
 sh_prog_rom_mem
  
  
  
    
 
      
        addr
        sh_prog_rom_mem_addr
        110
        
      
 
      
        cs
        sh_prog_rom_mem_cs
        reg
        
      
 
      
        wdata
        sh_prog_rom_mem_wdata
        150
        
      
 
      
        rdata
        sh_prog_rom_mem_rdata
        150
        
      
 
 
      
        rd
        sh_prog_rom_mem_rd
        
      
 
      
        wr
        sh_prog_rom_mem_wr
        
      
 
    
 
 
 
 
 

 
 
 

 
 

  elab_verilog
  102.1
  none
  :*Simulation:*
  ./tools/verilog/elab_verilog
    
    
      configuration
      default
    
    
      dest_dir
      io_ports
    
  

 
 
 

  gen_verilog
  104.0
  none
  common
  ./tools/verilog/gen_verilog
    
    
      destination
      top
    
    
      dest_dir
      ../verilog
    
  

 
 

 
 
 
 
 
  
 
    
      fs-common
 
      
        
        ../verilog/top.body
        verilogSourcefragment
      
 
    
 
 
    
      fs-sim
 
      
        
        ../verilog/copyright.v
        verilogSourceinclude
      
 
      
        
        ../verilog/common/top
        verilogSourcemodule
      
 
 
    
 
 
    
      fs-syn
 
      
        
        ../verilog/copyright.v
        verilogSourceinclude
      
 
      
        
        ../verilog/common/top
        verilogSourcemodule
      
 
 
    
 
 
 
 
 
 
 
  
 
 
 
 

 
      
 
 
              
              verilog
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="verilog"/>
              
              
 
 
 
 
 
 
              
              commoncommon
 
              Verilog
              
                     
                            fs-common
                     
              
 
 
              
              sim:*Simulation:*
 
              Verilog
              
                     
                            fs-sim
                     
              
 
              
              syn:*Synthesis:*
 
              Verilog
              
                     
                            fs-syn
                     
              
 
 
              
              doc
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="documentation"/>
              
              :*Documentation:*
              Verilog
              
 
 
 
      
 
 
 
 
 
 
 
 

 
 
 
 
 
 
 

 
 
 
  cpu
 
   
     io_reg
     0x8000
   
 
 
   
     data
     0x1000
   
 
   
     ext_mem
     0x4000
   
 
 
   
     prog_rom_mem
     0xc000
   
 
 
   
     sh_prog_rom_mem
     0xf000
   
 
 
 
 

 
 
 
 
 

 
  
    io_reg
    0x8000
    8
  
 
 
  
    data
    0x1000
    8
  
 
 
 
  
    mem
    0x0000
    8
  
 
 
 
 
  
    ext_mem
    0x4000
    8
  
 
 
  
    prog_rom_mem
    0xff00
    8
  
 
 
  
    sh_prog_rom_mem
    0xc000
    8
  
 
 
 

 
 
 
 
 
 


Browse

Tools

Subversion Repositories socgen

[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [logic/] [ip/] [micro_bus/] [rtl/] [xml/] [micro_bus_def.xml] - Blame information for rev 133

Line No.	Rev	Author	Line
1	131	jt_eaton
2
30
31			`xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"`
32			`xmlns:socgen="http://opencores.org"`
33			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
34			`xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009`
35			`http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">`
36
37			`opencores.org`
38			`logic`
39			`micro_bus`
40			`def default`
41
42
43
44
45
46			`slave_clk`
47
48
49
50
51
52			`clk`
53			`clk`
54
55
56
57
58
59			`slave_reset`
60
61
62
63
64
65			`reset`
66			`reset`
67
68
69
70
71
72			`master_enable`
73
74
75
76
77
78			`enable`
79			`enable`
80
81
82
83
84
85			`cpu`
86
87
88
89
90
91
92
93
94
95
96
97
98
99			`addr`
100			`addr_in`
101			`150`
102
103
104
105			`rdata`
106			`rdata_out`
107			`reg`
108			`150`
109
110
111
112
113
114
115			`wdata`
116			`wdata_in`
117			`70`
118
119
120
121
122
123			`wr`
124			`wr_in`
125
126
127
128
129
130			`rd`
131			`rd_in`
132
133
134
135
136
137
138
139
140
141
142			`mem`
143
144
145
146
147
148
149
150
151			`addr`
152			`mem_addr`
153			`150`
154
155
156
157
158			`cs`
159			`mem_cs`
160			`reg`
161
162
163
164
165			`wdata`
166			`mem_wdata`
167			`150`
168
169
170
171
172			`rdata`
173			`mem_rdata`
174			`150`
175
176
177
178
179
180			`wait`
181			`mem_wait`
182			`10`
183
184
185
186
187
188			`rd`
189			`mem_rd`
190
191
192
193
194			`wr`
195			`mem_wr`
196
197
198
199
200
201
202
203
204
205
206			`data`
207
208
209
210
211
212
213
214
215			`addr`
216			`data_addr`
217			`111`
218
219
220
221
222			`cs`
223			`data_cs`
224			`reg`
225
226
227
228
229			`wdata`
230			`data_wdata`
231			`150`
232
233
234
235
236			`rdata`
237			`data_rdata`
238			`150`
239
240
241
242
243
244			`be`
245			`data_be`
246			`10`
247
248
249
250
251
252			`rd`
253			`data_rd`
254
255
256
257
258			`wr`
259			`data_wr`
260
261
262
263
264
265
266
267
268
269			`io_reg`
270
271
272
273
274
275
276
277
278			`addr`
279			`io_reg_addr`
280	133	jt_eaton	`70`
281	131	jt_eaton
282
283
284
285			`cs`
286			`io_reg_cs`
287			`reg`
288
289
290
291
292			`wdata`
293			`io_reg_wdata`
294			`70`
295
296
297
298
299			`rdata`
300			`io_reg_rdata`
301			`150`
302
303
304
305
306
307			`wait`
308			`io_reg_wait`
309
310
311
312
313
314			`rd`
315			`io_reg_rd`
316
317
318
319
320			`wr`
321			`io_reg_wr`
322
323
324
325
326
327
328
329
330
331			`ext_mem`
332
333
334
335
336
337
338
339
340
341			`addr`
342			`ext_mem_addr`
343			`130`
344
345
346
347
348			`cs`
349			`ext_mem_cs`
350			`reg`
351
352
353
354
355			`wdata`
356			`ext_mem_wdata`
357			`150`
358
359
360
361
362			`rdata`
363			`ext_mem_rdata`
364			`150`
365
366
367
368
369
370			`wait`
371			`ext_mem_wait`
372
373
374
375
376
377			`rd`
378			`ext_mem_rd`
379
380
381
382
383			`wr`
384			`ext_mem_wr`
385
386
387
388
389
390
391
392
393
394
395
396			`prog_rom_mem`
397
398
399
400
401
402
403
404
405			`addr`
406			`prog_rom_mem_addr`
407			`110`
408
409
410
411
412			`cs`
413			`prog_rom_mem_cs`
414			`reg`
415
416
417
418
419			`wdata`
420			`prog_rom_mem_wdata`
421			`150`
422
423
424
425
426			`rdata`
427			`prog_rom_mem_rdata`
428			`150`
429
430
431
432
433
434			`rd`
435			`prog_rom_mem_rd`
436
437
438
439
440			`wr`
441			`prog_rom_mem_wr`
442
443
444
445
446
447
448
449
450
451
452			`sh_prog_rom_mem`
453
454
455
456
457
458
459			`addr`
460			`sh_prog_rom_mem_addr`
461			`110`
462
463
464
465
466			`cs`
467			`sh_prog_rom_mem_cs`
468			`reg`
469
470
471
472
473			`wdata`
474			`sh_prog_rom_mem_wdata`
475			`150`
476
477
478
479
480			`rdata`
481			`sh_prog_rom_mem_rdata`
482			`150`
483
484
485
486
487
488			`rd`
489			`sh_prog_rom_mem_rd`
490
491
492
493
494			`wr`
495			`sh_prog_rom_mem_wr`
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512	133	jt_eaton
513			`elab_verilog`
514			`102.1`
515			`none`
516			`:Simulation:`
517			`./tools/verilog/elab_verilog`
518
519
520			`configuration`
521			`default`
522
523
524			`dest_dir`
525			`io_ports`
526
527
528
529	131	jt_eaton
530
531	133	jt_eaton
532	131	jt_eaton
533			`gen_verilog`
534			`104.0`
535			`none`
536			`common`
537			`./tools/verilog/gen_verilog`
538
539
540			`destination`
541			`top`
542
543
544			`dest_dir`
545			`../verilog`
546
547
548
549
550
551
552
553
554	133	jt_eaton
555
556
557	131	jt_eaton
558
559
560			`fs-common`
561
562
563
564			`../verilog/top.body`
565			`verilogSourcefragment`
566
567
568
569
570
571
572			`fs-sim`
573
574
575
576			`../verilog/copyright.v`
577			`verilogSourceinclude`
578
579
580
581
582			`../verilog/common/top`
583			`verilogSourcemodule`
584
585
586
587
588
589
590
591			`fs-syn`
592
593
594
595			`../verilog/copyright.v`
596			`verilogSourceinclude`
597
598
599
600
601			`../verilog/common/top`
602			`verilogSourcemodule`
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625			`verilog`
626
627
628			`spirit:library="Testbench"`
629			`spirit:name="toolflow"`
630			`spirit:version="verilog"/>`
631
632
633
634
635
636
637
638
639
640			`commoncommon`
641
642			`Verilog`
643
644
645			`fs-common`
646
647
648
649
650
651			`sim:Simulation:`
652
653			`Verilog`
654
655
656			`fs-sim`
657
658
659
660
661			`syn:Synthesis:`
662
663			`Verilog`
664
665
666			`fs-syn`
667
668
669
670
671
672			`doc`
673
674
675			`spirit:library="Testbench"`
676			`spirit:name="toolflow"`
677			`spirit:version="documentation"/>`
678
679			`:Documentation:`
680			`Verilog`
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706			`cpu`
707
708
709			`io_reg`
710			`0x8000`
711
712
713
714
715			`data`
716			`0x1000`
717
718
719
720			`ext_mem`
721			`0x4000`
722
723
724
725
726			`prog_rom_mem`
727			`0xc000`
728
729
730
731
732			`sh_prog_rom_mem`
733			`0xf000`
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748			`io_reg`
749			`0x8000`
750			`8`
751
752
753
754
755			`data`
756			`0x1000`
757			`8`
758
759
760
761
762
763			`mem`
764			`0x0000`
765			`8`
766
767
768
769
770
771
772			`ext_mem`
773			`0x4000`
774			`8`
775
776
777
778
779			`prog_rom_mem`
780			`0xff00`
781			`8`
782
783
784
785
786			`sh_prog_rom_mem`
787			`0xc000`
788			`8`
789
790
791
792
793
794
795
796
797
798
799
800