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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [logic/] [ip/] [micro_bus/] [sim/] [testbenches/] [xml/] [micro_bus_def_tb.xml] - Blame information for rev 131

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xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
 
opencores.org
logic
micro_bus
def_tb
 
 
 

 
 
 

  gen_verilog
  104.0
  none
  common
  ./tools/verilog/gen_verilog
    
    
      destination
      top.tb
    
    
      dest_dir
      ../verilog
    
    
      top
    
  

 
 
 

 
 
 
 
 
 
 
 

 

    ADDR_WIDTH16

 
 
       
 
 
 
              
              Params
              
                
                                   spirit:library="logic"
                                   spirit:name="micro_bus"
                                   spirit:version="def_dut.params"/>
             
              
 
              
              Bfm
              
                                   spirit:library="logic"
                                   spirit:name="micro_bus"
                                   spirit:version="bfm.design"/>
              
 
 
              
              icarus
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="icarus"/>
              
              
 
 
 
 
 
              
              commoncommon
              Verilog
              
                     
                            fs-common
                     
              
 
 
              
              sim:*Simulation:*
              Verilog
              
                     
                            fs-sim
                     
              
 
 
              
              lint:*Lint:*
              Verilog
              
                     
                            fs-lint
                     
              
 
 
      
 
 
 
 
 
 

 
 
 
 
 

 
   
      fs-common
 
      
        
        ../verilog/tb.ext
        verilogSourcefragment
      
 
 
   
 
   
      fs-sim
 
 
      
        
        ../verilog/common/top.tb
        verilogSourcemodule
      
 
 
 
   
 
 
 
   
      fs-lint
 
 
      
        
        ../verilog/common/top.tb
        verilogSourcemodule
      
 
 
 
   
 
 
 
 

 
 
 
 
 

 
 
 
 
 

Line No.	Rev	Author	Line
1	131	jt_eaton
2
30
31			`xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"`
32			`xmlns:socgen="http://opencores.org"`
33			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
34			`xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009`
35			`http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">`
36
37			`opencores.org`
38			`logic`
39			`micro_bus`
40			`def_tb`
41
42
43
44
45
46
47
48
49			`gen_verilog`
50			`104.0`
51			`none`
52			`common`
53			`./tools/verilog/gen_verilog`
54
55
56			`destination`
57			`top.tb`
58
59
60			`dest_dir`
61			`../verilog`
62
63
64			`top`
65
66
67
68
69
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71
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73
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75
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83			`ADDR_WIDTH16`
84
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92			`Params`
93
94
95			`spirit:library="logic"`
96			`spirit:name="micro_bus"`
97			`spirit:version="def_dut.params"/>`
98
99
100
101
102			`Bfm`
103
104			`spirit:library="logic"`
105			`spirit:name="micro_bus"`
106			`spirit:version="bfm.design"/>`
107
108
109
110
111			`icarus`
112
113
114			`spirit:library="Testbench"`
115			`spirit:name="toolflow"`
116			`spirit:version="icarus"/>`
117
118
119
120
121
122
123
124
125			`commoncommon`
126			`Verilog`
127
128
129			`fs-common`
130
131
132
133
134
135			`sim:Simulation:`
136			`Verilog`
137
138
139			`fs-sim`
140
141
142
143
144
145			`lint:Lint:`
146			`Verilog`
147
148
149			`fs-lint`
150
151
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155
156
157
158
159
160
161
162
163
164
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167
168
169
170			`fs-common`
171
172
173
174			`../verilog/tb.ext`
175			`verilogSourcefragment`
176
177
178
179
180
181
182			`fs-sim`
183
184
185
186
187			`../verilog/common/top.tb`
188			`verilogSourcemodule`
189
190
191
192
193
194
195
196
197
198			`fs-lint`
199
200
201
202
203			`../verilog/common/top.tb`
204			`verilogSourcemodule`
205
206
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209
210
211
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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [logic/] [ip/] [micro_bus/] [sim/] [testbenches/] [xml/] [micro_bus_def_tb.xml] - Blame information for rev 131