URL https://opencores.org/ocsvn/socgen/socgen/trunk

Subversion Repositories socgen

[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [logic/] [ip/] [ps2_interface/] [rtl/] [verilog/] [fsm] - Blame information for rev 131

Details | Compare with Previous | View Log


 
 
module  `VARIANT`FSM
 
 
#(parameter NUMBITS=11)
 
(
 
 
input  wire        ps2_idle,
input  wire        ps2_clk_fall,
input  wire        clk,
input  wire        reset,
input  wire [3:0]  bit_count,
input  wire        write,
input  wire        usec_delay_done,
input  wire        force_startbit,
 
output reg         load_tx_data,
output reg         ps2_clk_oe,
output reg         busy,
output reg         shift_frame,
output reg         enable_usec_delay
 
);
 
 
 
`define fsm_idle                       4'b0000
`define fsm_rx_clk                     4'b0001
`define fsm_rx_clk_fall               4'b0010
`define fsm_rx_data_ready              4'b0011
 
`define fsm_tx_force_clk_low           4'b1000
`define fsm_tx_force_startbit          4'b1001
`define fsm_tx_startbit                4'b1010
`define fsm_tx_clk_fall                4'b1011
`define fsm_tx_wait_data               4'b1100
`define fsm_tx_wait_ack                4'b1101
`define fsm_tx_wait_idle               4'b1110
 
 
 
 
 
reg  [3:0]         state;
reg  [3:0]         next_state;
reg                next_ps2_clk_oe;
 
 
 
 
 
always@(posedge clk)
     begin
      if(reset)
        begin
         busy               <= 0;
         state              <= `fsm_idle;
         ps2_clk_oe         <= 0;
         load_tx_data       <= 0;
         shift_frame        <= 0;
         enable_usec_delay  <= 0;
     end
      else
        begin
         busy               <= !(next_state == `fsm_idle);
         state              <=   next_state;
         ps2_clk_oe         <=   next_ps2_clk_oe;
         load_tx_data       <= ( state == `fsm_tx_force_clk_low);
         shift_frame        <= ((next_state == `fsm_rx_clk_fall)|| (next_state == `fsm_tx_clk_fall));
         enable_usec_delay  <= (!write && ((next_state == `fsm_tx_force_startbit) || (next_state == `fsm_tx_force_clk_low)));
     end
    end
 
 
 
 
always @(*)
begin
   next_state         = `fsm_idle;
   next_ps2_clk_oe    = 0;
   case (state)
 
   (`fsm_idle ):
              begin
              if(ps2_clk_fall )             next_state            = `fsm_rx_clk_fall;
              else
              if(write)                     next_state            = `fsm_tx_force_clk_low;
              else                          next_state            = `fsm_idle;
              end
 
   (`fsm_rx_clk_fall):                      next_state            = `fsm_rx_clk;
 
 
   (`fsm_rx_clk):
               begin
               if(bit_count == NUMBITS)     next_state            = `fsm_rx_data_ready;
               else
               if(ps2_clk_fall)             next_state            = `fsm_rx_clk_fall;
               else                         next_state            = `fsm_rx_clk;
               end
 
 
 
   (`fsm_rx_data_ready):                    next_state            = `fsm_idle;
 
 
 
 
 
 
 
   (`fsm_tx_force_clk_low):
              begin
                                            next_ps2_clk_oe       = 1;
              if(force_startbit )           next_state            = `fsm_tx_force_startbit;
              else                          next_state            = `fsm_tx_force_clk_low;
              end
 
 
   (`fsm_tx_force_startbit):
              begin
 
                                            next_ps2_clk_oe     = 1;
              if(usec_delay_done)           next_state          = `fsm_tx_startbit;
              else                          next_state          = `fsm_tx_force_startbit;
              end
 
 
   (`fsm_tx_startbit):
               begin
                                            next_ps2_clk_oe     = 0;
               if(ps2_clk_fall)             next_state          = `fsm_tx_clk_fall;
               else                         next_state          = `fsm_tx_startbit;
               end
 
 
 
 
  (`fsm_tx_clk_fall):
               begin
                                           next_state           = `fsm_tx_wait_data;
               end
 
 
 
 
 
  (`fsm_tx_wait_data):
           begin
 
               if(bit_count == NUMBITS-1)
                         begin
                                           next_state           = `fsm_tx_wait_ack;
                         end
               else
                         begin
                         if(ps2_clk_fall)  next_state           = `fsm_tx_clk_fall;
                         else              next_state           = `fsm_tx_wait_data;
                         end
 
           end
 
 
 
 
     (`fsm_tx_wait_ack):
               begin
               if(ps2_clk_fall)            next_state     = `fsm_tx_wait_idle;
               else                        next_state     = `fsm_tx_wait_ack;
               end
 
 
 
 
     (`fsm_tx_wait_idle):
               begin
               if(ps2_idle)                next_state      = `fsm_idle;
               else                        next_state      = `fsm_tx_wait_idle;
               end
 
 
           default :                       next_state  = `fsm_idle;
 
 
 
 
     endcase // case (state)
 
 
     end
 
 
 
 
 
 
 
endmodule
 
 

Browse

Tools

Subversion Repositories socgen

[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [logic/] [ip/] [ps2_interface/] [rtl/] [verilog/] [fsm] - Blame information for rev 131

Line No.	Rev	Author	Line
1	131	jt_eaton
2
3			module `VARIANT`FSM
4
5
6			`#(parameter NUMBITS=11)`
7
8			`(`
9
10
11			`input wire ps2_idle,`
12			`input wire ps2_clk_fall,`
13			`input wire clk,`
14			`input wire reset,`
15			`input wire [3:0] bit_count,`
16			`input wire write,`
17			`input wire usec_delay_done,`
18			`input wire force_startbit,`
19
20			`output reg load_tx_data,`
21			`output reg ps2_clk_oe,`
22			`output reg busy,`
23			`output reg shift_frame,`
24			`output reg enable_usec_delay`
25
26			`);`
27
28
29
30			`define fsm_idle 4'b0000
31			`define fsm_rx_clk 4'b0001
32			`define fsm_rx_clk_fall 4'b0010
33			`define fsm_rx_data_ready 4'b0011
34
35			`define fsm_tx_force_clk_low 4'b1000
36			`define fsm_tx_force_startbit 4'b1001
37			`define fsm_tx_startbit 4'b1010
38			`define fsm_tx_clk_fall 4'b1011
39			`define fsm_tx_wait_data 4'b1100
40			`define fsm_tx_wait_ack 4'b1101
41			`define fsm_tx_wait_idle 4'b1110
42
43
44
45
46
47			`reg [3:0] state;`
48			`reg [3:0] next_state;`
49			`reg next_ps2_clk_oe;`
50
51
52
53
54
55			`always@(posedge clk)`
56			`begin`
57			`if(reset)`
58			`begin`
59			`busy <= 0;`
60			state <= `fsm_idle;
61			`ps2_clk_oe <= 0;`
62			`load_tx_data <= 0;`
63			`shift_frame <= 0;`
64			`enable_usec_delay <= 0;`
65			`end`
66			`else`
67			`begin`
68			busy <= !(next_state == `fsm_idle);
69			`state <= next_state;`
70			`ps2_clk_oe <= next_ps2_clk_oe;`
71			load_tx_data <= ( state == `fsm_tx_force_clk_low);
72			shift_frame <= ((next_state == `fsm_rx_clk_fall)\|\| (next_state == `fsm_tx_clk_fall));
73			enable_usec_delay <= (!write && ((next_state == `fsm_tx_force_startbit) \|\| (next_state == `fsm_tx_force_clk_low)));
74			`end`
75			`end`
76
77
78
79
80			`always @(*)`
81			`begin`
82			next_state = `fsm_idle;
83			`next_ps2_clk_oe = 0;`
84			`case (state)`
85
86			(`fsm_idle ):
87			`begin`
88			if(ps2_clk_fall ) next_state = `fsm_rx_clk_fall;
89			`else`
90			if(write) next_state = `fsm_tx_force_clk_low;
91			else next_state = `fsm_idle;
92			`end`
93
94			(`fsm_rx_clk_fall): next_state = `fsm_rx_clk;
95
96
97			(`fsm_rx_clk):
98			`begin`
99			if(bit_count == NUMBITS) next_state = `fsm_rx_data_ready;
100			`else`
101			if(ps2_clk_fall) next_state = `fsm_rx_clk_fall;
102			else next_state = `fsm_rx_clk;
103			`end`
104
105
106
107			(`fsm_rx_data_ready): next_state = `fsm_idle;
108
109
110
111
112
113
114
115			(`fsm_tx_force_clk_low):
116			`begin`
117			`next_ps2_clk_oe = 1;`
118			if(force_startbit ) next_state = `fsm_tx_force_startbit;
119			else next_state = `fsm_tx_force_clk_low;
120			`end`
121
122
123			(`fsm_tx_force_startbit):
124			`begin`
125
126			`next_ps2_clk_oe = 1;`
127			if(usec_delay_done) next_state = `fsm_tx_startbit;
128			else next_state = `fsm_tx_force_startbit;
129			`end`
130
131
132			(`fsm_tx_startbit):
133			`begin`
134			`next_ps2_clk_oe = 0;`
135			if(ps2_clk_fall) next_state = `fsm_tx_clk_fall;
136			else next_state = `fsm_tx_startbit;
137			`end`
138
139
140
141
142			(`fsm_tx_clk_fall):
143			`begin`
144			next_state = `fsm_tx_wait_data;
145			`end`
146
147
148
149
150
151			(`fsm_tx_wait_data):
152			`begin`
153
154			`if(bit_count == NUMBITS-1)`
155			`begin`
156			next_state = `fsm_tx_wait_ack;
157			`end`
158			`else`
159			`begin`
160			if(ps2_clk_fall) next_state = `fsm_tx_clk_fall;
161			else next_state = `fsm_tx_wait_data;
162			`end`
163
164			`end`
165
166
167
168
169			(`fsm_tx_wait_ack):
170			`begin`
171			if(ps2_clk_fall) next_state = `fsm_tx_wait_idle;
172			else next_state = `fsm_tx_wait_ack;
173			`end`
174
175
176
177
178			(`fsm_tx_wait_idle):
179			`begin`
180			if(ps2_idle) next_state = `fsm_idle;
181			else next_state = `fsm_tx_wait_idle;
182			`end`
183
184
185			default : next_state = `fsm_idle;
186
187
188
189
190			`endcase // case (state)`
191
192
193			`end`
194
195
196
197
198
199
200
201			`endmodule`
202
203