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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [logic/] [ip/] [ps2_interface/] [rtl/] [xml/] [ps2_interface_def.xml] - Blame information for rev 133

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xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
 
opencores.org
logic
ps2_interface
def  default
 
 

 
 slave_clk
  
  
  
    
      
        clk
        clk
      
    
 
 
 
 slave_reset
  
  
  
    
      
        reset
        reset
      
    
 
 
 
 
 
 ps2
  
  
  
    
 
      
        clk_pad_oe
        ps2_clk_pad_oe
      
 
 
      
        clk_pad_in
        ps2_clk_pad_in
      
 
 
      
        data_pad_oe
        ps2_data_pad_oe
      
 
 
      
        data_pad_in
        ps2_data_pad_in
      
 
 
    
 
 
 
 
 
 
 
 

 
 
 
 

 
 
 
 

  elab_verilog
  102.1
  none
  :*Simulation:*
  ./tools/verilog/elab_verilog
    
    
      dest_dir
      io_ports
    
  

 
 
 
 
 
 
 

  gen_verilog_sim
  104.0
  none
  :*Simulation:*
  ./tools/verilog/gen_verilog
    
    
      destination
      top.out.sim
    
    
      dest_dir
      ../verilog
    
  

 

  gen_verilog_syn
  104.0
  none
  :*Synthesis:*
  ./tools/verilog/gen_verilog
    
    
      destination
      top.out.syn
    
    
      dest_dir
      ../verilog
    
  

 
 
 

 
 
 
  
 
    
      fs-sim
 
      
        
        ../verilog/copyright.v
        verilogSourceinclude
      
 
      
        
        ../verilog/sim/top.out.sim
        verilogSourcemodule
      
 
      
        fsm
        ../verilog/fsm
        verilogSourcemodule
      
 
      
        
        ../verilog/top.body
        verilogSourcefragment
      
 
      
        
        ../verilog/top.sim
        verilogSourcefragment
      
 
 
 
    
 
    
      fs-syn
 
      
        
        ../verilog/copyright.v
        verilogSourceinclude
      
 
      
        
        ../verilog/syn/top.out.syn
        verilogSourcemodule
      
 
      
        fsm
        ../verilog/fsm
        verilogSourcemodule
      
 
      
        
        ../verilog/top.body
        verilogSourcefragment
      
 
 
    
 
 
 
 
  
 
 
 

       
 
              
              Hierarchical
 
              
                                   spirit:library="logic"
                                   spirit:name="ps2_interface"
                                   spirit:version="def.design"/>
              
 
 
              
              verilog
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="verilog"/>
              
              
 
 
 
 
 
              
              sim:*Simulation:*
 
              Verilog
              
                     
                            fs-sim
                     
              
 
 
              
              syn:*Synthesis:*
 
              Verilog
              
                     
                            fs-syn
                     
              
 
 
              
              doc
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="documentation"/>
              
              :*Documentation:*
              Verilog
              
 
      
 
 
 
 
 
 
 
 

FREQ24
CLK_HOLD_DELAY100
DATA_SETUP_DELAY20
DEBOUNCE_DELAY4'b1111

 
 

 
busy
wire
out

 
tx_data
wire
in
70

 
tx_write
wire
in

 
rx_data
reg
out
70

 
rx_read
reg
out

 
rx_full
reg
out

 
rx_parity_error
reg
out

 
rx_parity_rcv
reg
out

 
rx_parity_cal
reg
out

 
rx_frame_error
reg
out

 
rx_clear
wire
in

 
tx_buffer_empty
wire
out

 
tx_ack_error
regx
out

 
 
 

 
 
 
 
 
 


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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [logic/] [ip/] [ps2_interface/] [rtl/] [xml/] [ps2_interface_def.xml] - Blame information for rev 133

Line No.	Rev	Author	Line
1	131	jt_eaton
2
30
31			`xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"`
32			`xmlns:socgen="http://opencores.org"`
33			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
34			`xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009`
35			`http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">`
36
37			`opencores.org`
38			`logic`
39			`ps2_interface`
40			`def default`
41
42
43
44
45			`slave_clk`
46
47
48
49
50
51			`clk`
52			`clk`
53
54
55
56
57
58			`slave_reset`
59
60
61
62
63
64			`reset`
65			`reset`
66
67
68
69
70
71
72
73			`ps2`
74
75
76
77
78
79
80			`clk_pad_oe`
81			`ps2_clk_pad_oe`
82
83
84
85
86			`clk_pad_in`
87			`ps2_clk_pad_in`
88
89
90
91
92			`data_pad_oe`
93			`ps2_data_pad_oe`
94
95
96
97
98			`data_pad_in`
99			`ps2_data_pad_in`
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122	133	jt_eaton
123			`elab_verilog`
124			`102.1`
125			`none`
126			`:Simulation:`
127			`./tools/verilog/elab_verilog`
128
129
130			`dest_dir`
131			`io_ports`
132
133
134
135	131	jt_eaton
136
137
138	133	jt_eaton
139
140
141
142	131	jt_eaton
143			`gen_verilog_sim`
144			`104.0`
145			`none`
146			`:Simulation:`
147			`./tools/verilog/gen_verilog`
148
149
150			`destination`
151			`top.out.sim`
152
153
154			`dest_dir`
155			`../verilog`
156
157
158
159
160
161			`gen_verilog_syn`
162			`104.0`
163			`none`
164			`:Synthesis:`
165			`./tools/verilog/gen_verilog`
166
167
168			`destination`
169			`top.out.syn`
170
171
172			`dest_dir`
173			`../verilog`
174
175
176
177
178
179
180
181
182
183
184
185
186
187			`fs-sim`
188
189
190
191			`../verilog/copyright.v`
192			`verilogSourceinclude`
193
194
195
196
197			`../verilog/sim/top.out.sim`
198			`verilogSourcemodule`
199
200
201
202			`fsm`
203			`../verilog/fsm`
204			`verilogSourcemodule`
205
206
207
208
209			`../verilog/top.body`
210			`verilogSourcefragment`
211
212
213
214
215			`../verilog/top.sim`
216			`verilogSourcefragment`
217
218
219
220
221
222
223
224			`fs-syn`
225
226
227
228			`../verilog/copyright.v`
229			`verilogSourceinclude`
230
231
232
233
234			`../verilog/syn/top.out.syn`
235			`verilogSourcemodule`
236
237
238
239			`fsm`
240			`../verilog/fsm`
241			`verilogSourcemodule`
242
243
244
245
246			`../verilog/top.body`
247			`verilogSourcefragment`
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264			`Hierarchical`
265
266
267			`spirit:library="logic"`
268			`spirit:name="ps2_interface"`
269			`spirit:version="def.design"/>`
270
271
272
273
274			`verilog`
275
276
277			`spirit:library="Testbench"`
278			`spirit:name="toolflow"`
279			`spirit:version="verilog"/>`
280
281
282
283
284
285
286
287
288			`sim:Simulation:`
289
290			`Verilog`
291
292
293			`fs-sim`
294
295
296
297
298
299			`syn:Synthesis:`
300
301			`Verilog`
302
303
304			`fs-syn`
305
306
307
308
309
310			`doc`
311
312
313			`spirit:library="Testbench"`
314			`spirit:name="toolflow"`
315			`spirit:version="documentation"/>`
316
317			`:Documentation:`
318			`Verilog`
319
320
321
322
323
324
325
326
327
328
329
330
331			`FREQ24`
332			`CLK_HOLD_DELAY100`
333			`DATA_SETUP_DELAY20`
334			`DEBOUNCE_DELAY4'b1111`
335
336
337
338
339
340			`busy`
341			`wire`
342			`out`
343
344
345			`tx_data`
346			`wire`
347			`in`
348			`70`
349
350
351			`tx_write`
352			`wire`
353			`in`
354
355
356			`rx_data`
357			`reg`
358			`out`
359			`70`
360
361
362			`rx_read`
363			`reg`
364			`out`
365
366
367			`rx_full`
368			`reg`
369			`out`
370
371
372			`rx_parity_error`
373			`reg`
374			`out`
375
376
377			`rx_parity_rcv`
378			`reg`
379			`out`
380
381
382			`rx_parity_cal`
383			`reg`
384			`out`
385
386
387			`rx_frame_error`
388			`reg`
389			`out`
390
391
392			`rx_clear`
393			`wire`
394			`in`
395
396
397			`tx_buffer_empty`
398			`wire`
399			`out`
400
401
402			`tx_ack_error`
403			`regx`
404			`out`
405
406
407
408
409
410
411
412
413
414
415
416