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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [logic/] [ip/] [serial_rcvr/] [rtl/] [xml/] [serial_rcvr_def.xml] - Blame information for rev 131

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xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
 
opencores.org
logic
serial_rcvr
def  default
 
 

 
 slave_clk
  
  
  
    
      
        clk
        clk
      
    
 
 
 
 slave_reset
  
  
  
    
      
        reset
        reset
      
    
 
 

 
 
 
 

 
 
 
 
 
 

  gen_verilog
  104.0
  none
  common
  ./tools/verilog/gen_verilog
   
    
      destination
      top
    
    
      dest_dir
      ../verilog
    
  

 
 
 

 
  
 
    
      fs-common
 
      
        
        ../verilog/top.body
        verilogSourcefragment
      
 
      
        
        ../verilog/no_fifo
        verilogSourcefragment
      
 
 
 
    
 
    
      fs-sim
 
      
        
        ../verilog/copyright.v
        verilogSourceinclude
      
 
      
        
        ../verilog/common/top
        verilogSourcemodule
      
 
 
    
 
 
 
    
      fs-syn
 
      
        
        ../verilog/copyright.v
        verilogSourceinclude
      
 
      
        
        ../verilog/common/top
        verilogSourcemodule
      
 
 
 
    
 
 
 
 
  
 
 

       
 
              
              Hierarchical
 
              
                                   spirit:library="logic"
                                   spirit:name="serial_rcvr"
                                   spirit:version="def.design"/>
              
 
              
              verilog
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="verilog"/>
              
              
 
 
 
 
 
              
              commoncommon
              Verilog
              
                     
                            fs-common
                     
              
 
 
 
              
              sim:*Simulation:*
              Verilog
              
                     
                            fs-sim
                     
              
 
 
 
              
              syn:*Synthesis:*
              Verilog
              
                     
                            fs-syn
                     
              
 
 
 
              
              doc
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="documentation"/>
              
              :*Documentation:*
              Verilog
              
 
 
 
      
 
 
 
 

WIDTH8
SIZE4
SAMPLE4'b0111
START_VALUE1'b0
STOP_VALUE1'b1

 

 
 
edge_enable
wire
in

 
parity_enable
wire
in

 
parity_type
wire
in

 
parity_force
wire
in

 
 
 
 
pad_in
wire
in

 
rcv_stb
wire
in

 
data_out
wire
out
WIDTH-10

 
parity_error
wire
out

 
stop_error
wire
out

 
data_avail
wire
out

 

 

 
 
 
 
 
 
 


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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [logic/] [ip/] [serial_rcvr/] [rtl/] [xml/] [serial_rcvr_def.xml] - Blame information for rev 131

Line No.	Rev	Author	Line
1	131	jt_eaton
2
30
31			`xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"`
32			`xmlns:socgen="http://opencores.org"`
33			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
34			`xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009`
35			`http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">`
36
37			`opencores.org`
38			`logic`
39			`serial_rcvr`
40			`def default`
41
42
43
44
45			`slave_clk`
46
47
48
49
50
51			`clk`
52			`clk`
53
54
55
56
57
58			`slave_reset`
59
60
61
62
63
64			`reset`
65			`reset`
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83			`gen_verilog`
84			`104.0`
85			`none`
86			`common`
87			`./tools/verilog/gen_verilog`
88
89
90			`destination`
91			`top`
92
93
94			`dest_dir`
95			`../verilog`
96
97
98
99
100
101
102
103
104
105
106
107			`fs-common`
108
109
110
111			`../verilog/top.body`
112			`verilogSourcefragment`
113
114
115
116
117			`../verilog/no_fifo`
118			`verilogSourcefragment`
119
120
121
122
123
124
125
126			`fs-sim`
127
128
129
130			`../verilog/copyright.v`
131			`verilogSourceinclude`
132
133
134
135
136			`../verilog/common/top`
137			`verilogSourcemodule`
138
139
140
141
142
143
144
145
146			`fs-syn`
147
148
149
150			`../verilog/copyright.v`
151			`verilogSourceinclude`
152
153
154
155
156			`../verilog/common/top`
157			`verilogSourcemodule`
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174			`Hierarchical`
175
176
177			`spirit:library="logic"`
178			`spirit:name="serial_rcvr"`
179			`spirit:version="def.design"/>`
180
181
182
183			`verilog`
184
185
186			`spirit:library="Testbench"`
187			`spirit:name="toolflow"`
188			`spirit:version="verilog"/>`
189
190
191
192
193
194
195
196
197			`commoncommon`
198			`Verilog`
199
200
201			`fs-common`
202
203
204
205
206
207
208			`sim:Simulation:`
209			`Verilog`
210
211
212			`fs-sim`
213
214
215
216
217
218
219			`syn:Synthesis:`
220			`Verilog`
221
222
223			`fs-syn`
224
225
226
227
228
229
230			`doc`
231
232
233			`spirit:library="Testbench"`
234			`spirit:name="toolflow"`
235			`spirit:version="documentation"/>`
236
237			`:Documentation:`
238			`Verilog`
239
240
241
242
243
244
245
246
247
248
249			`WIDTH8`
250			`SIZE4`
251			`SAMPLE4'b0111`
252			`START_VALUE1'b0`
253			`STOP_VALUE1'b1`
254
255
256
257
258
259			`edge_enable`
260			`wire`
261			`in`
262
263
264			`parity_enable`
265			`wire`
266			`in`
267
268
269			`parity_type`
270			`wire`
271			`in`
272
273
274			`parity_force`
275			`wire`
276			`in`
277
278
279
280
281
282			`pad_in`
283			`wire`
284			`in`
285
286
287			`rcv_stb`
288			`wire`
289			`in`
290
291
292			`data_out`
293			`wire`
294			`out`
295			`WIDTH-10`
296
297
298			`parity_error`
299			`wire`
300			`out`
301
302
303			`stop_error`
304			`wire`
305			`out`
306
307
308			`data_avail`
309			`wire`
310			`out`
311
312
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