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Subversion Repositories socgen

[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [logic/] [ip/] [serial_rcvr/] [sim/] [testbenches/] [verilog/] [top.ext] - Blame information for rev 131

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reg  R_edge_enable     ;
reg  R_parity_enable   ;
reg  R_parity_type     ;
reg  R_parity_force    ;
reg  R_start_value     ;
reg  R_pad_in          ;
reg  R_rcv_stb         ;
 
 
assign  edge_enable     =  R_edge_enable     ;
assign  parity_enable   =  R_parity_enable   ;
assign  parity_type     =  R_parity_type     ;
assign  parity_force    =  R_parity_force    ;
assign  start_value     =  R_start_value     ;
assign  pad_in          =  serial            ;
assign  rcv_stb         =  R_rcv_stb         ;
 
 
assign STOP = 1'b0;
assign BAD = 1'b0;
 
 
 
 
 

Line No.	Rev	Author	Line
1	131	jt_eaton
2
3
4
5			`reg R_edge_enable ;`
6			`reg R_parity_enable ;`
7			`reg R_parity_type ;`
8			`reg R_parity_force ;`
9			`reg R_start_value ;`
10			`reg R_pad_in ;`
11			`reg R_rcv_stb ;`
12
13
14			`assign edge_enable = R_edge_enable ;`
15			`assign parity_enable = R_parity_enable ;`
16			`assign parity_type = R_parity_type ;`
17			`assign parity_force = R_parity_force ;`
18			`assign start_value = R_start_value ;`
19			`assign pad_in = serial ;`
20			`assign rcv_stb = R_rcv_stb ;`
21
22
23			`assign STOP = 1'b0;`
24			`assign BAD = 1'b0;`
25
26
27
28
29

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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [logic/] [ip/] [serial_rcvr/] [sim/] [testbenches/] [verilog/] [top.ext] - Blame information for rev 131