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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [logic/] [ip/] [serial_rcvr/] [sim/] [testbenches/] [xml/] [serial_rcvr_fifo_tb.xml] - Blame information for rev 131

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xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
 
opencores.org
logic
serial_rcvr
fifo_tb
 
 
 
 
 
 

 
 
 

  gen_verilog
  104.0
  none
  common
  ./tools/verilog/gen_verilog
    
    
      destination
      top.tb.fifo
    
    
      dest_dir
      ../verilog
    
    
      top
    
  

 
 
 
 
 

 
 
 
 

 
 
 
 
       
 
              
              Params
              
              
                                   spirit:library="logic"
                                   spirit:name="serial_rcvr"
                                   spirit:version="fifo_dut.params"/>
             
              
 
 
              
              Bfm
              
                                   spirit:library="logic"
                                   spirit:name="serial_rcvr"
                                   spirit:version="bfm.design"/>
              
 
 
              
              icarus
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="icarus"/>
              
              
 
 
 
 
              
              commoncommon
              Verilog
              
                     
                            fs-common
                     
              
 
 
              
              sim:*Simulation:*
              Verilog
              
                     
                            fs-sim
                     
              
 
 
              
              lint:*Lint:*
              Verilog
              
                     
                            fs-lint
                     
              
 
 
 
 
      
 
 
 
 

 
 
 
 
  
 
    
      fs-common
 
      
        
        ../verilog/top.ext
        verilogSourcefragment
      
 
 
    
 
 
    
      fs-sim
 
      
        
        ../verilog/common/top.tb.fifo
        verilogSourcemodule
      
 
 
 
 
 
    
 
 
 
    
      fs-lint
 
      
        
        ../verilog/common/top.tb.fifo
        verilogSourcemodule
      
 
 
 
 
 
    
 
 
 
 
 
  
 
 
 
 
 
 


Line No.	Rev	Author	Line
1	131	jt_eaton
2
30
31			`xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"`
32			`xmlns:socgen="http://opencores.org"`
33			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
34			`xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009`
35			`http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">`
36
37			`opencores.org`
38			`logic`
39			`serial_rcvr`
40			`fifo_tb`
41
42
43
44
45
46
47
48
49
50
51
52			`gen_verilog`
53			`104.0`
54			`none`
55			`common`
56			`./tools/verilog/gen_verilog`
57
58
59			`destination`
60			`top.tb.fifo`
61
62
63			`dest_dir`
64			`../verilog`
65
66
67			`top`
68
69
70
71
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73
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75
76
77
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81
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89			`Params`
90
91
92			`spirit:library="logic"`
93			`spirit:name="serial_rcvr"`
94			`spirit:version="fifo_dut.params"/>`
95
96
97
98
99
100			`Bfm`
101
102			`spirit:library="logic"`
103			`spirit:name="serial_rcvr"`
104			`spirit:version="bfm.design"/>`
105
106
107
108
109			`icarus`
110
111
112			`spirit:library="Testbench"`
113			`spirit:name="toolflow"`
114			`spirit:version="icarus"/>`
115
116
117
118
119
120
121
122			`commoncommon`
123			`Verilog`
124
125
126			`fs-common`
127
128
129
130
131
132			`sim:Simulation:`
133			`Verilog`
134
135
136			`fs-sim`
137
138
139
140
141
142			`lint:Lint:`
143			`Verilog`
144
145
146			`fs-lint`
147
148
149
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151
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153
154
155
156
157
158
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161
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164
165
166			`fs-common`
167
168
169
170			`../verilog/top.ext`
171			`verilogSourcefragment`
172
173
174
175
176
177
178
179			`fs-sim`
180
181
182
183			`../verilog/common/top.tb.fifo`
184			`verilogSourcemodule`
185
186
187
188
189
190
191
192
193
194
195
196			`fs-lint`
197
198
199
200			`../verilog/common/top.tb.fifo`
201			`verilogSourcemodule`
202
203
204
205
206
207
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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [logic/] [ip/] [serial_rcvr/] [sim/] [testbenches/] [xml/] [serial_rcvr_fifo_tb.xml] - Blame information for rev 131