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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [logic/] [ip/] [uart/] [rtl/] [verilog/] [top.body.tx] - Blame information for rev 131

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assign  txd_break_n  = !txd_break ;
 
 
 
always@(posedge clk)
  if(reset)            rts_pad_out  <= 1'b0;
  else                 rts_pad_out  <= rts_in;
 
always@(posedge clk)
  if(reset)            cts_out      <= 1'b0;
  else                 cts_out      <= cts_pad_in;
 
 
 
 
 
generate
 
if(DIV == 0)
  begin
assign    baud_clk_div = baud_clk;
  end
else
begin
cde_divider_def
#(.SIZE(DIV_SIZE))
baud_divider  (
         .clk             ( clk          ),
         .reset           ( reset        ),
         .divider_in      ( divider_in   ),
         .enable          ( baud_clk     ),
         .divider_out     ( baud_clk_div )
         );
end
 
endgenerate
 
 
 
 
 
 
 
 
 
 
 
 
always@(posedge clk)
  if(reset)
    begin
       xmit_start     <= 1'b0;
    end
  else
  if( !fifo_empty &&   cde_buffer_empty &&  !xmit_start )
    begin
       xmit_start     <= 1'b1;
    end
  else
    begin
       xmit_start     <= 1'b0;
    end
 
assign txd_buffer_empty =      !fifo_full;
 
assign fifo_pop =  !fifo_empty &&   cde_buffer_empty && ! xmit_start;
 
 
 

Line No.	Rev	Author	Line
1	131	jt_eaton	`assign txd_break_n = !txd_break ;`
2
3
4
5			`always@(posedge clk)`
6			`if(reset) rts_pad_out <= 1'b0;`
7			`else rts_pad_out <= rts_in;`
8
9			`always@(posedge clk)`
10			`if(reset) cts_out <= 1'b0;`
11			`else cts_out <= cts_pad_in;`
12
13
14
15
16
17			`generate`
18
19			`if(DIV == 0)`
20			`begin`
21			`assign baud_clk_div = baud_clk;`
22			`end`
23			`else`
24			`begin`
25			`cde_divider_def`
26			`#(.SIZE(DIV_SIZE))`
27			`baud_divider (`
28			`.clk ( clk ),`
29			`.reset ( reset ),`
30			`.divider_in ( divider_in ),`
31			`.enable ( baud_clk ),`
32			`.divider_out ( baud_clk_div )`
33			`);`
34			`end`
35
36			`endgenerate`
37
38
39
40
41
42
43
44
45
46
47
48
49			`always@(posedge clk)`
50			`if(reset)`
51			`begin`
52			`xmit_start <= 1'b0;`
53			`end`
54			`else`
55			`if( !fifo_empty && cde_buffer_empty && !xmit_start )`
56			`begin`
57			`xmit_start <= 1'b1;`
58			`end`
59			`else`
60			`begin`
61			`xmit_start <= 1'b0;`
62			`end`
63
64			`assign txd_buffer_empty = !fifo_full;`
65
66			`assign fifo_pop = !fifo_empty && cde_buffer_empty && ! xmit_start;`
67
68
69

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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [logic/] [ip/] [uart/] [rtl/] [verilog/] [top.body.tx] - Blame information for rev 131