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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [logic/] [ip/] [uart/] [rtl/] [xml/] [uart_def.xml] - Blame information for rev 133

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xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
 
opencores.org
logic
uart
def  default
 

 
 slave_clk
  
  
  
    
      
        clk
        clk
      
    
 
 
 
 slave_reset
  
  
  
    
      
        reset
        reset
      
    
 
 
 
 
 
 uart
  
  
  
    
 
      
        txd_pad_out
        txd_pad_out
      
 
 
      
        rxd_pad_in
        rxd_pad_in
      
 
 
    
 
 
 
 rxd_data_avail
  
  
  
    
 
      
        IRQ
        rxd_data_avail_IRQ
      
 
    
 
 
 
 
 txd_buffer_empty
  
  
  
    
 
      
        NIRQ
        txd_buffer_empty_NIRQ
      
 
    
 
 
 
 
 

 
 
 

 
 

  elab_verilog
  102.1
  none
  :*Simulation:*
  ./tools/verilog/elab_verilog
    
    
      dest_dir
      io_ports
    
  

 
 
 
 
 

  gen_verilog_sim
  104.0
  none
  :*Simulation:*
  ./tools/verilog/gen_verilog
  
    
      destination
      top.out.sim
    
    
      dest_dir
      ../verilog
    
  

 
 

  gen_verilog_syn
  104.0
  none
  :*Synthesis:*
  ./tools/verilog/gen_verilog
    
    
      destination
      top.out.syn
    
    
      dest_dir
      ../verilog
    
  

 
 
 
 

 
 
  
 
 
 
 
 
    
      fs-sim
 
      
        
        ../verilog/copyright.v
        verilogSourceinclude
      
 
 
      
        
        ../verilog/sim/top.out.sim
        verilogSourcemodule
      
 
      
        
        ../verilog/top.body
        verilogSourcefragment
      
 
      
        
        ../verilog/top.sim
        verilogSourcefragment
      
 
 
    
 
 
 
    
      fs-syn
 
      
        
        ../verilog/copyright.v
        verilogSourceinclude
      
 
 
      
        
        ../verilog/syn/top.out.syn
        verilogSourcemodule
      
 
      
        
        ../verilog/top.body
        verilogSourcefragment
      
 
 
 
 
    
 
 
 
 
 
  
 
 
 
 

       
 
              
              Hierarchical
 
              
                                   spirit:library="logic"
                                   spirit:name="uart"
                                   spirit:version="def.design"/>
              
 
 
              
              verilog
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="verilog"/>
              
              
 
 
 
 
 
              
              sim:*Simulation:*
 
              Verilog
              
                     
                            fs-sim
                     
              
 
              
              syn:*Synthesis:*
 
              Verilog
              
                     
                            fs-syn
                     
              
 
 
              
              doc
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="documentation"/>
              
              :*Documentation:*
              Verilog
              
 
 
 
      
 
 
 
 
 
 
 

PRESCALE5'b01100
PRE_SIZE5
SIZE8
DIV0
DIV_SIZE4

 
 
 
 

 
parity_enable
wire
in

 
divider_in
wire
in
DIV_SIZE-10

 
cts_pad_in
wire
in

 
rts_pad_out
reg
out

 
 
cts_out
reg
out

 
rts_in
wire
in

 
txd_parity
wire
in

 
txd_force_parity
wire
in

 
txd_load
wire
in

 
txd_break
wire
in

 
txd_data_in
wire
in
SIZE-10

 
txd_buffer_empty
wire
out

 
rxd_data_avail_stb
wire
in

 
rxd_data_avail
wire
out

 
rxd_parity
wire
in

 
rxd_force_parity
wire
in

 
rxd_data_out
wire
out
SIZE-10

 
rxd_parity_error
wire
out

 
rxd_stop_error
wire
out

 

 

 
 
 
 
 


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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [logic/] [ip/] [uart/] [rtl/] [xml/] [uart_def.xml] - Blame information for rev 133

Line No.	Rev	Author	Line
1	131	jt_eaton
2
30
31			`xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"`
32			`xmlns:socgen="http://opencores.org"`
33			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
34			`xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009`
35			`http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">`
36
37			`opencores.org`
38			`logic`
39			`uart`
40			`def default`
41
42
43
44			`slave_clk`
45
46
47
48
49
50			`clk`
51			`clk`
52
53
54
55
56
57			`slave_reset`
58
59
60
61
62
63			`reset`
64			`reset`
65
66
67
68
69
70
71
72			`uart`
73
74
75
76
77
78
79			`txd_pad_out`
80			`txd_pad_out`
81
82
83
84
85			`rxd_pad_in`
86			`rxd_pad_in`
87
88
89
90
91
92
93
94			`rxd_data_avail`
95
96
97
98
99
100
101			`IRQ`
102			`rxd_data_avail_IRQ`
103
104
105
106
107
108
109
110			`txd_buffer_empty`
111
112
113
114
115
116
117			`NIRQ`
118			`txd_buffer_empty_NIRQ`
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134	133	jt_eaton
135			`elab_verilog`
136			`102.1`
137			`none`
138			`:Simulation:`
139			`./tools/verilog/elab_verilog`
140
141
142			`dest_dir`
143			`io_ports`
144
145
146
147	131	jt_eaton
148
149
150
151
152
153			`gen_verilog_sim`
154			`104.0`
155			`none`
156			`:Simulation:`
157			`./tools/verilog/gen_verilog`
158
159
160			`destination`
161			`top.out.sim`
162
163
164			`dest_dir`
165			`../verilog`
166
167
168
169
170
171
172			`gen_verilog_syn`
173			`104.0`
174			`none`
175			`:Synthesis:`
176			`./tools/verilog/gen_verilog`
177
178
179			`destination`
180			`top.out.syn`
181
182
183			`dest_dir`
184			`../verilog`
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202			`fs-sim`
203
204
205
206			`../verilog/copyright.v`
207			`verilogSourceinclude`
208
209
210
211
212
213			`../verilog/sim/top.out.sim`
214			`verilogSourcemodule`
215
216
217
218
219			`../verilog/top.body`
220			`verilogSourcefragment`
221
222
223
224
225			`../verilog/top.sim`
226			`verilogSourcefragment`
227
228
229
230
231
232
233
234
235			`fs-syn`
236
237
238
239			`../verilog/copyright.v`
240			`verilogSourceinclude`
241
242
243
244
245
246			`../verilog/syn/top.out.syn`
247			`verilogSourcemodule`
248
249
250
251
252			`../verilog/top.body`
253			`verilogSourcefragment`
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274			`Hierarchical`
275
276
277			`spirit:library="logic"`
278			`spirit:name="uart"`
279			`spirit:version="def.design"/>`
280
281
282
283
284			`verilog`
285
286
287			`spirit:library="Testbench"`
288			`spirit:name="toolflow"`
289			`spirit:version="verilog"/>`
290
291
292
293
294
295
296
297
298			`sim:Simulation:`
299
300			`Verilog`
301
302
303			`fs-sim`
304
305
306
307
308			`syn:Synthesis:`
309
310			`Verilog`
311
312
313			`fs-syn`
314
315
316
317
318
319			`doc`
320
321
322			`spirit:library="Testbench"`
323			`spirit:name="toolflow"`
324			`spirit:version="documentation"/>`
325
326			`:Documentation:`
327			`Verilog`
328
329
330
331
332
333
334
335
336
337
338
339
340
341			`PRESCALE5'b01100`
342			`PRE_SIZE5`
343			`SIZE8`
344			`DIV0`
345			`DIV_SIZE4`
346
347
348
349
350
351
352
353			`parity_enable`
354			`wire`
355			`in`
356
357
358			`divider_in`
359			`wire`
360			`in`
361			`DIV_SIZE-10`
362
363
364			`cts_pad_in`
365			`wire`
366			`in`
367
368
369			`rts_pad_out`
370			`reg`
371			`out`
372
373
374
375			`cts_out`
376			`reg`
377			`out`
378
379
380			`rts_in`
381			`wire`
382			`in`
383
384
385			`txd_parity`
386			`wire`
387			`in`
388
389
390			`txd_force_parity`
391			`wire`
392			`in`
393
394
395			`txd_load`
396			`wire`
397			`in`
398
399
400			`txd_break`
401			`wire`
402			`in`
403
404
405			`txd_data_in`
406			`wire`
407			`in`
408			`SIZE-10`
409
410
411			`txd_buffer_empty`
412			`wire`
413			`out`
414
415
416			`rxd_data_avail_stb`
417			`wire`
418			`in`
419
420
421			`rxd_data_avail`
422			`wire`
423			`out`
424
425
426			`rxd_parity`
427			`wire`
428			`in`
429
430
431			`rxd_force_parity`
432			`wire`
433			`in`
434
435
436			`rxd_data_out`
437			`wire`
438			`out`
439			`SIZE-10`
440
441
442			`rxd_parity_error`
443			`wire`
444			`out`
445
446
447			`rxd_stop_error`
448			`wire`
449			`out`
450
451
452
453
454
455
456
457
458
459
460