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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [logic/] [ip/] [uart/] [rtl/] [xml/] [uart_rx.xml] - Blame information for rev 131

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xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
 
opencores.org
logic
uart
rx  default
 

 
 slave_clk
  
  
  
    
      
        clk
        clk
      
    
 
 
 
 slave_reset
  
  
  
    
      
        reset
        reset
      
    
 
 
 
 
 
 
 uart
  
  
  
    
 
      
        txd_pad_out
        txd_pad_out
      
 
 
      
        rxd_pad_in
        rxd_pad_in
      
 
 
    
 
 
 
 
 rxd_data_avail
  
  
  
    
 
      
        IRQ
        rxd_data_avail_IRQ
      
 
    
 
 
 

 
 
 

 
 
 
 
 

  gen_verilog_sim
  104.0
  none
  :*Simulation:*
  ./tools/verilog/gen_verilog
    
    
      destination
      top.rx.sim
    
    
      dest_dir
      ../verilog
    
  

 

  gen_verilog_syn
  104.0
  none
  :*Synthesis:*
  ./tools/verilog/gen_verilog
    
    
      destination
      top.rx.syn
    
    
      dest_dir
      ../verilog
    
  

 
 
 

 
 
 
 
  
 
    
      fs-sim
 
      
        
        ../verilog/copyright.v
        verilogSourceinclude
      
 
 
      
        
        ../verilog/sim/top.rx.sim
        verilogSourcemodule
      
 
      
        
        ../verilog/top.body
        verilogSourcefragment
      
 
      
        
        ../verilog/top.sim
        verilogSourcefragment
      
 
 
 
    
 
 
    
      fs-syn
 
      
        
        ../verilog/copyright.v
        verilogSourceinclude
      
 
 
      
        
        ../verilog/syn/top.rx.syn
        verilogSourcemodule
      
 
      
        
        ../verilog/top.body
        verilogSourcefragment
      
 
 
    
 
 
 
 
 
 
  
 
 
 
 
 

       
 
              
              Hierarchical
 
              
                                   spirit:library="logic"
                                   spirit:name="uart"
                                   spirit:version="rx.design"/>
              
 
 
              
              verilog
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="verilog"/>
              
              
 
 
 
 
 
 
              
              sim:*Simulation:*
 
              Verilog
              
                     
                            fs-sim
                     
              
 
              
              syn:*Synthesis:*
 
              Verilog
              
                     
                            fs-syn
                     
              
 
              
              doc
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="documentation"/>
              
              :*Documentation:*
              Verilog
              
 
 
 
      
 
 
 
 
 
 
 

PRESCALE5'b01100
PRE_SIZE5
SIZE8
DIV0
DIV_SIZE4
RX_FIFO_SIZE3
RX_FIFO_WORDS8

 
 
 
 

 
parity_enable
wire
in

 
divider_in
wire
in
DIV_SIZE-10

 
cts_pad_in
wire
in

 
rts_pad_out
reg
out

 
 
 
cts_out
reg
out

 
rts_in
wire
in

 
txd_parity
wire
in

 
txd_force_parity
wire
in

 
txd_load
wire
in

 
txd_break
wire
in

 
txd_data_in
wire
in
SIZE-10

 
txd_buffer_empty
wire
out

 
rxd_data_avail_stb
wire
in

 
rxd_data_avail
wire
out

 
rxd_parity
wire
in

 
rxd_force_parity
wire
in

 
rxd_data_out
wire
out
SIZE-10

 
rxd_parity_error
wire
out

 
rxd_stop_error
wire
out

 

 

 
 
 
 
 
 


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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [logic/] [ip/] [uart/] [rtl/] [xml/] [uart_rx.xml] - Blame information for rev 131

Line No.	Rev	Author	Line
1	131	jt_eaton
2
30
31			`xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"`
32			`xmlns:socgen="http://opencores.org"`
33			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
34			`xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009`
35			`http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">`
36
37			`opencores.org`
38			`logic`
39			`uart`
40			`rx default`
41
42
43
44			`slave_clk`
45
46
47
48
49
50			`clk`
51			`clk`
52
53
54
55
56
57			`slave_reset`
58
59
60
61
62
63			`reset`
64			`reset`
65
66
67
68
69
70
71
72
73			`uart`
74
75
76
77
78
79
80			`txd_pad_out`
81			`txd_pad_out`
82
83
84
85
86			`rxd_pad_in`
87			`rxd_pad_in`
88
89
90
91
92
93
94
95
96			`rxd_data_avail`
97
98
99
100
101
102
103			`IRQ`
104			`rxd_data_avail_IRQ`
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122			`gen_verilog_sim`
123			`104.0`
124			`none`
125			`:Simulation:`
126			`./tools/verilog/gen_verilog`
127
128
129			`destination`
130			`top.rx.sim`
131
132
133			`dest_dir`
134			`../verilog`
135
136
137
138
139
140			`gen_verilog_syn`
141			`104.0`
142			`none`
143			`:Synthesis:`
144			`./tools/verilog/gen_verilog`
145
146
147			`destination`
148			`top.rx.syn`
149
150
151			`dest_dir`
152			`../verilog`
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167			`fs-sim`
168
169
170
171			`../verilog/copyright.v`
172			`verilogSourceinclude`
173
174
175
176
177
178			`../verilog/sim/top.rx.sim`
179			`verilogSourcemodule`
180
181
182
183
184			`../verilog/top.body`
185			`verilogSourcefragment`
186
187
188
189
190			`../verilog/top.sim`
191			`verilogSourcefragment`
192
193
194
195
196
197
198
199
200			`fs-syn`
201
202
203
204			`../verilog/copyright.v`
205			`verilogSourceinclude`
206
207
208
209
210
211			`../verilog/syn/top.rx.syn`
212			`verilogSourcemodule`
213
214
215
216
217			`../verilog/top.body`
218			`verilogSourcefragment`
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239			`Hierarchical`
240
241
242			`spirit:library="logic"`
243			`spirit:name="uart"`
244			`spirit:version="rx.design"/>`
245
246
247
248
249			`verilog`
250
251
252			`spirit:library="Testbench"`
253			`spirit:name="toolflow"`
254			`spirit:version="verilog"/>`
255
256
257
258
259
260
261
262
263
264			`sim:Simulation:`
265
266			`Verilog`
267
268
269			`fs-sim`
270
271
272
273
274			`syn:Synthesis:`
275
276			`Verilog`
277
278
279			`fs-syn`
280
281
282
283
284			`doc`
285
286
287			`spirit:library="Testbench"`
288			`spirit:name="toolflow"`
289			`spirit:version="documentation"/>`
290
291			`:Documentation:`
292			`Verilog`
293
294
295
296
297
298
299
300
301
302
303
304
305
306			`PRESCALE5'b01100`
307			`PRE_SIZE5`
308			`SIZE8`
309			`DIV0`
310			`DIV_SIZE4`
311			`RX_FIFO_SIZE3`
312			`RX_FIFO_WORDS8`
313
314
315
316
317
318
319
320			`parity_enable`
321			`wire`
322			`in`
323
324
325			`divider_in`
326			`wire`
327			`in`
328			`DIV_SIZE-10`
329
330
331			`cts_pad_in`
332			`wire`
333			`in`
334
335
336			`rts_pad_out`
337			`reg`
338			`out`
339
340
341
342
343			`cts_out`
344			`reg`
345			`out`
346
347
348			`rts_in`
349			`wire`
350			`in`
351
352
353			`txd_parity`
354			`wire`
355			`in`
356
357
358			`txd_force_parity`
359			`wire`
360			`in`
361
362
363			`txd_load`
364			`wire`
365			`in`
366
367
368			`txd_break`
369			`wire`
370			`in`
371
372
373			`txd_data_in`
374			`wire`
375			`in`
376			`SIZE-10`
377
378
379			`txd_buffer_empty`
380			`wire`
381			`out`
382
383
384			`rxd_data_avail_stb`
385			`wire`
386			`in`
387
388
389			`rxd_data_avail`
390			`wire`
391			`out`
392
393
394			`rxd_parity`
395			`wire`
396			`in`
397
398
399			`rxd_force_parity`
400			`wire`
401			`in`
402
403
404			`rxd_data_out`
405			`wire`
406			`out`
407			`SIZE-10`
408
409
410			`rxd_parity_error`
411			`wire`
412			`out`
413
414
415			`rxd_stop_error`
416			`wire`
417			`out`
418
419
420
421
422
423
424
425
426
427
428
429