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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [logic/] [ip/] [uart/] [rtl/] [xml/] [uart_rx.xml] - Blame information for rev 133

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xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
 
opencores.org
logic
uart
rx  default
 

 
 slave_clk
  
  
  
    
      
        clk
        clk
      
    
 
 
 
 slave_reset
  
  
  
    
      
        reset
        reset
      
    
 
 
 
 
 
 
 uart
  
  
  
    
 
      
        txd_pad_out
        txd_pad_out
      
 
 
      
        rxd_pad_in
        rxd_pad_in
      
 
 
    
 
 
 
 
 rxd_data_avail
  
  
  
    
 
      
        IRQ
        rxd_data_avail_IRQ
      
 
    
 
 
 

 
 
 

 
 
 

  elab_verilog
  102.1
  none
  :*Simulation:*
  ./tools/verilog/elab_verilog
    
    
      dest_dir
      io_ports
    
  

 
 
 
 

  gen_verilog_sim
  104.0
  none
  :*Simulation:*
  ./tools/verilog/gen_verilog
    
    
      destination
      top.rx.sim
    
    
      dest_dir
      ../verilog
    
  

 

  gen_verilog_syn
  104.0
  none
  :*Synthesis:*
  ./tools/verilog/gen_verilog
    
    
      destination
      top.rx.syn
    
    
      dest_dir
      ../verilog
    
  

 
 
 

 
 
 
 
  
 
    
      fs-sim
 
      
        
        ../verilog/copyright.v
        verilogSourceinclude
      
 
 
      
        
        ../verilog/sim/top.rx.sim
        verilogSourcemodule
      
 
      
        
        ../verilog/top.body
        verilogSourcefragment
      
 
      
        
        ../verilog/top.sim
        verilogSourcefragment
      
 
 
 
    
 
 
    
      fs-syn
 
      
        
        ../verilog/copyright.v
        verilogSourceinclude
      
 
 
      
        
        ../verilog/syn/top.rx.syn
        verilogSourcemodule
      
 
      
        
        ../verilog/top.body
        verilogSourcefragment
      
 
 
    
 
 
 
 
 
 
  
 
 
 
 
 

       
 
              
              Hierarchical
 
              
                                   spirit:library="logic"
                                   spirit:name="uart"
                                   spirit:version="rx.design"/>
              
 
 
              
              verilog
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="verilog"/>
              
              
 
 
 
 
 
 
              
              sim:*Simulation:*
 
              Verilog
              
                     
                            fs-sim
                     
              
 
              
              syn:*Synthesis:*
 
              Verilog
              
                     
                            fs-syn
                     
              
 
              
              doc
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="documentation"/>
              
              :*Documentation:*
              Verilog
              
 
 
 
      
 
 
 
 
 
 
 

PRESCALE5'b01100
PRE_SIZE5
SIZE8
DIV0
DIV_SIZE4
RX_FIFO_SIZE3
RX_FIFO_WORDS8

 
 
 
 

 
parity_enable
wire
in

 
divider_in
wire
in
DIV_SIZE-10

 
cts_pad_in
wire
in

 
rts_pad_out
reg
out

 
 
 
cts_out
reg
out

 
rts_in
wire
in

 
txd_parity
wire
in

 
txd_force_parity
wire
in

 
txd_load
wire
in

 
txd_break
wire
in

 
txd_data_in
wire
in
SIZE-10

 
txd_buffer_empty
wire
out

 
rxd_data_avail_stb
wire
in

 
rxd_data_avail
wire
out

 
rxd_parity
wire
in

 
rxd_force_parity
wire
in

 
rxd_data_out
wire
out
SIZE-10

 
rxd_parity_error
wire
out

 
rxd_stop_error
wire
out

 

 

 
 
 
 
 
 


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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [logic/] [ip/] [uart/] [rtl/] [xml/] [uart_rx.xml] - Blame information for rev 133

Line No.	Rev	Author	Line
1	131	jt_eaton
2
30
31			`xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"`
32			`xmlns:socgen="http://opencores.org"`
33			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
34			`xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009`
35			`http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">`
36
37			`opencores.org`
38			`logic`
39			`uart`
40			`rx default`
41
42
43
44			`slave_clk`
45
46
47
48
49
50			`clk`
51			`clk`
52
53
54
55
56
57			`slave_reset`
58
59
60
61
62
63			`reset`
64			`reset`
65
66
67
68
69
70
71
72
73			`uart`
74
75
76
77
78
79
80			`txd_pad_out`
81			`txd_pad_out`
82
83
84
85
86			`rxd_pad_in`
87			`rxd_pad_in`
88
89
90
91
92
93
94
95
96			`rxd_data_avail`
97
98
99
100
101
102
103			`IRQ`
104			`rxd_data_avail_IRQ`
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119	133	jt_eaton
120			`elab_verilog`
121			`102.1`
122			`none`
123			`:Simulation:`
124			`./tools/verilog/elab_verilog`
125
126
127			`dest_dir`
128			`io_ports`
129
130
131
132	131	jt_eaton
133
134	133	jt_eaton
135
136	131	jt_eaton
137			`gen_verilog_sim`
138			`104.0`
139			`none`
140			`:Simulation:`
141			`./tools/verilog/gen_verilog`
142
143
144			`destination`
145			`top.rx.sim`
146
147
148			`dest_dir`
149			`../verilog`
150
151
152
153
154
155			`gen_verilog_syn`
156			`104.0`
157			`none`
158			`:Synthesis:`
159			`./tools/verilog/gen_verilog`
160
161
162			`destination`
163			`top.rx.syn`
164
165
166			`dest_dir`
167			`../verilog`
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182			`fs-sim`
183
184
185
186			`../verilog/copyright.v`
187			`verilogSourceinclude`
188
189
190
191
192
193			`../verilog/sim/top.rx.sim`
194			`verilogSourcemodule`
195
196
197
198
199			`../verilog/top.body`
200			`verilogSourcefragment`
201
202
203
204
205			`../verilog/top.sim`
206			`verilogSourcefragment`
207
208
209
210
211
212
213
214
215			`fs-syn`
216
217
218
219			`../verilog/copyright.v`
220			`verilogSourceinclude`
221
222
223
224
225
226			`../verilog/syn/top.rx.syn`
227			`verilogSourcemodule`
228
229
230
231
232			`../verilog/top.body`
233			`verilogSourcefragment`
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254			`Hierarchical`
255
256
257			`spirit:library="logic"`
258			`spirit:name="uart"`
259			`spirit:version="rx.design"/>`
260
261
262
263
264			`verilog`
265
266
267			`spirit:library="Testbench"`
268			`spirit:name="toolflow"`
269			`spirit:version="verilog"/>`
270
271
272
273
274
275
276
277
278
279			`sim:Simulation:`
280
281			`Verilog`
282
283
284			`fs-sim`
285
286
287
288
289			`syn:Synthesis:`
290
291			`Verilog`
292
293
294			`fs-syn`
295
296
297
298
299			`doc`
300
301
302			`spirit:library="Testbench"`
303			`spirit:name="toolflow"`
304			`spirit:version="documentation"/>`
305
306			`:Documentation:`
307			`Verilog`
308
309
310
311
312
313
314
315
316
317
318
319
320
321			`PRESCALE5'b01100`
322			`PRE_SIZE5`
323			`SIZE8`
324			`DIV0`
325			`DIV_SIZE4`
326			`RX_FIFO_SIZE3`
327			`RX_FIFO_WORDS8`
328
329
330
331
332
333
334
335			`parity_enable`
336			`wire`
337			`in`
338
339
340			`divider_in`
341			`wire`
342			`in`
343			`DIV_SIZE-10`
344
345
346			`cts_pad_in`
347			`wire`
348			`in`
349
350
351			`rts_pad_out`
352			`reg`
353			`out`
354
355
356
357
358			`cts_out`
359			`reg`
360			`out`
361
362
363			`rts_in`
364			`wire`
365			`in`
366
367
368			`txd_parity`
369			`wire`
370			`in`
371
372
373			`txd_force_parity`
374			`wire`
375			`in`
376
377
378			`txd_load`
379			`wire`
380			`in`
381
382
383			`txd_break`
384			`wire`
385			`in`
386
387
388			`txd_data_in`
389			`wire`
390			`in`
391			`SIZE-10`
392
393
394			`txd_buffer_empty`
395			`wire`
396			`out`
397
398
399			`rxd_data_avail_stb`
400			`wire`
401			`in`
402
403
404			`rxd_data_avail`
405			`wire`
406			`out`
407
408
409			`rxd_parity`
410			`wire`
411			`in`
412
413
414			`rxd_force_parity`
415			`wire`
416			`in`
417
418
419			`rxd_data_out`
420			`wire`
421			`out`
422			`SIZE-10`
423
424
425			`rxd_parity_error`
426			`wire`
427			`out`
428
429
430			`rxd_stop_error`
431			`wire`
432			`out`
433
434
435
436
437
438
439
440
441
442
443
444