URL https://opencores.org/ocsvn/socgen/socgen/trunk

Subversion Repositories socgen

[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [logic/] [ip/] [uart/] [rtl/] [xml/] [uart_tx.xml] - Blame information for rev 131

Go to most recent revision | Details | Compare with Previous | View Log





xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
 
opencores.org
logic
uart
tx  default
 
 

 
 slave_clk
  
  
  
    
      
        clk
        clk
      
    
 
 
 
 slave_reset
  
  
  
    
      
        reset
        reset
      
    
 
 
 
 
 uart
  
  
  
    
 
      
        txd_pad_out
        txd_pad_out
      
 
 
      
        rxd_pad_in
        rxd_pad_in
      
 
 
    
 
 
 
 
 
 txd_buffer_empty
  
  
  
    
 
      
        NIRQ
        txd_buffer_empty_NIRQ
      
 
    
 
 
 
 

 
 

 
 
 
 

  gen_verilog_sim
  104.0
  none
  :*Simulation:*
  ./tools/verilog/gen_verilog
    
    
      destination
      top.tx.sim
    
    
      dest_dir
      ../verilog
    
  

 

  gen_verilog_syn
  104.0
  none
  :*Synthesis:*
  ./tools/verilog/gen_verilog
    
    
      destination
      top.tx.syn
    
    
      dest_dir
      ../verilog
    
  

 
 
 

 
 
  
 
    
      fs-sim
 
      
        
        ../verilog/copyright.v
        verilogSourceinclude
      
 
 
      
        
        ../verilog/sim/top.tx.sim
        verilogSourcemodule
      
 
      
        
        ../verilog/top.body.tx
        verilogSourcefragment
      
 
      
        
        ../verilog/top.sim
        verilogSourcefragment
      
 
 
 
    
 
    
      fs-syn
 
      
        
        ../verilog/copyright.v
        verilogSourceinclude
      
 
 
      
        
        ../verilog/syn/top.tx.syn
        verilogSourcemodule
      
 
      
        
        ../verilog/top.body.tx
        verilogSourcefragment
      
 
 
    
 
 
 
 
 
  
 
 
 
 
 
 

       
 
              
              Hierarchical
 
              
                                   spirit:library="logic"
                                   spirit:name="uart"
                                   spirit:version="tx.design"/>
              
 
 
              
              verilog
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="verilog"/>
              
              
 
 
 
 
 
 
              
              sim:*Simulation:*
 
              Verilog
              
                     
                            fs-sim
                     
              
 
              
              syn:*Synthesis:*
 
              Verilog
              
                     
                            fs-syn
                     
              
 
 
              
              doc
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="documentation"/>
              
              :*Documentation:*
              Verilog
              
 
 
      
 
 
 
 
 
 
 

PRESCALE5'b01100
PRE_SIZE5
SIZE8
DIV0
DIV_SIZE4
TX_FIFO_SIZE3
TX_FIFO_WORDS8

 
 
 
 

 
 
parity_enable
wire
in

 
divider_in
wire
in
DIV_SIZE-10

 
cts_pad_in
wire
in

 
rts_pad_out
reg
out

 
 
 
cts_out
reg
out

 
rts_in
wire
in

 
txd_parity
wire
in

 
txd_force_parity
wire
in

 
txd_load
wire
in

 
txd_break
wire
in

 
txd_data_in
wire
in
SIZE-10

 
txd_buffer_empty
wire
out

 
rxd_data_avail_stb
wire
in

 
rxd_data_avail
wire
out

 
rxd_parity
wire
in

 
rxd_force_parity
wire
in

 
rxd_data_out
wire
out
SIZE-10

 
rxd_parity_error
wire
out

 
rxd_stop_error
wire
out

 

 

 
 
 
 
 


Browse

Tools

Subversion Repositories socgen

[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [logic/] [ip/] [uart/] [rtl/] [xml/] [uart_tx.xml] - Blame information for rev 131

Line No.	Rev	Author	Line
1	131	jt_eaton
2
30
31			`xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"`
32			`xmlns:socgen="http://opencores.org"`
33			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
34			`xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009`
35			`http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">`
36
37			`opencores.org`
38			`logic`
39			`uart`
40			`tx default`
41
42
43
44
45			`slave_clk`
46
47
48
49
50
51			`clk`
52			`clk`
53
54
55
56
57
58			`slave_reset`
59
60
61
62
63
64			`reset`
65			`reset`
66
67
68
69
70
71
72			`uart`
73
74
75
76
77
78
79			`txd_pad_out`
80			`txd_pad_out`
81
82
83
84
85			`rxd_pad_in`
86			`rxd_pad_in`
87
88
89
90
91
92
93
94
95
96			`txd_buffer_empty`
97
98
99
100
101
102
103			`NIRQ`
104			`txd_buffer_empty_NIRQ`
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121			`gen_verilog_sim`
122			`104.0`
123			`none`
124			`:Simulation:`
125			`./tools/verilog/gen_verilog`
126
127
128			`destination`
129			`top.tx.sim`
130
131
132			`dest_dir`
133			`../verilog`
134
135
136
137
138
139			`gen_verilog_syn`
140			`104.0`
141			`none`
142			`:Synthesis:`
143			`./tools/verilog/gen_verilog`
144
145
146			`destination`
147			`top.tx.syn`
148
149
150			`dest_dir`
151			`../verilog`
152
153
154
155
156
157
158
159
160
161
162
163
164			`fs-sim`
165
166
167
168			`../verilog/copyright.v`
169			`verilogSourceinclude`
170
171
172
173
174
175			`../verilog/sim/top.tx.sim`
176			`verilogSourcemodule`
177
178
179
180
181			`../verilog/top.body.tx`
182			`verilogSourcefragment`
183
184
185
186
187			`../verilog/top.sim`
188			`verilogSourcefragment`
189
190
191
192
193
194
195
196			`fs-syn`
197
198
199
200			`../verilog/copyright.v`
201			`verilogSourceinclude`
202
203
204
205
206
207			`../verilog/syn/top.tx.syn`
208			`verilogSourcemodule`
209
210
211
212
213			`../verilog/top.body.tx`
214			`verilogSourcefragment`
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235			`Hierarchical`
236
237
238			`spirit:library="logic"`
239			`spirit:name="uart"`
240			`spirit:version="tx.design"/>`
241
242
243
244
245			`verilog`
246
247
248			`spirit:library="Testbench"`
249			`spirit:name="toolflow"`
250			`spirit:version="verilog"/>`
251
252
253
254
255
256
257
258
259
260			`sim:Simulation:`
261
262			`Verilog`
263
264
265			`fs-sim`
266
267
268
269
270			`syn:Synthesis:`
271
272			`Verilog`
273
274
275			`fs-syn`
276
277
278
279
280
281			`doc`
282
283
284			`spirit:library="Testbench"`
285			`spirit:name="toolflow"`
286			`spirit:version="documentation"/>`
287
288			`:Documentation:`
289			`Verilog`
290
291
292
293
294
295
296
297
298
299
300
301
302			`PRESCALE5'b01100`
303			`PRE_SIZE5`
304			`SIZE8`
305			`DIV0`
306			`DIV_SIZE4`
307			`TX_FIFO_SIZE3`
308			`TX_FIFO_WORDS8`
309
310
311
312
313
314
315
316
317			`parity_enable`
318			`wire`
319			`in`
320
321
322			`divider_in`
323			`wire`
324			`in`
325			`DIV_SIZE-10`
326
327
328			`cts_pad_in`
329			`wire`
330			`in`
331
332
333			`rts_pad_out`
334			`reg`
335			`out`
336
337
338
339
340			`cts_out`
341			`reg`
342			`out`
343
344
345			`rts_in`
346			`wire`
347			`in`
348
349
350			`txd_parity`
351			`wire`
352			`in`
353
354
355			`txd_force_parity`
356			`wire`
357			`in`
358
359
360			`txd_load`
361			`wire`
362			`in`
363
364
365			`txd_break`
366			`wire`
367			`in`
368
369
370			`txd_data_in`
371			`wire`
372			`in`
373			`SIZE-10`
374
375
376			`txd_buffer_empty`
377			`wire`
378			`out`
379
380
381			`rxd_data_avail_stb`
382			`wire`
383			`in`
384
385
386			`rxd_data_avail`
387			`wire`
388			`out`
389
390
391			`rxd_parity`
392			`wire`
393			`in`
394
395
396			`rxd_force_parity`
397			`wire`
398			`in`
399
400
401			`rxd_data_out`
402			`wire`
403			`out`
404			`SIZE-10`
405
406
407			`rxd_parity_error`
408			`wire`
409			`out`
410
411
412			`rxd_stop_error`
413			`wire`
414			`out`
415
416
417
418
419
420
421
422
423
424
425