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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [logic/] [ip/] [uart/] [sim/] [testbenches/] [xml/] [uart_tx_lint.xml] - Blame information for rev 131

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xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
 
opencores.org
logic
uart
tx_lint
 
 
 

 
 
       
 
 
 
              
              Dut
              
              
                                   spirit:library="logic"
                                   spirit:name="uart"
                                   spirit:version="tx_dut.params"/>
              
 
              
 
 
 
              
              lint
              :*Lint:*
              Verilog
              fs-lint
              
 
 
 
              
              rtl_check
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="rtl_check"/>
              
              
 
      
 
 
 
 
 
 
 

 
 
 
 
 
  
 
 
 
    
      fs-lint
 
      
        
        ../verilog/lint/uart_tx_lint
        verilogSourcemodule
      
 
    
 
 
 
 
  
 
 
 
 
 
 


Line No.	Rev	Author	Line
1	131	jt_eaton
2
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31			`xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"`
32			`xmlns:socgen="http://opencores.org"`
33			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
34			`xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009`
35			`http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">`
36
37			`opencores.org`
38			`logic`
39			`uart`
40			`tx_lint`
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52			`Dut`
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55			`spirit:library="logic"`
56			`spirit:name="uart"`
57			`spirit:version="tx_dut.params"/>`
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65			`lint`
66			`:Lint:`
67			`Verilog`
68			`fs-lint`
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74			`rtl_check`
75
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77			`spirit:library="Testbench"`
78			`spirit:name="toolflow"`
79			`spirit:version="rtl_check"/>`
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102			`fs-lint`
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106			`../verilog/lint/uart_tx_lint`
107			`verilogSourcemodule`
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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [logic/] [ip/] [uart/] [sim/] [testbenches/] [xml/] [uart_tx_lint.xml] - Blame information for rev 131