This component takes the opencores opb_vga_char_display_nodac project and makes it socgen compatible. The original project checked in by Timmothy Pearson in Oct 2007 consisted of a single module that added a asic vga interface to a microblaze system. It had no documentation or test suite and could only work in xilinx spartan parts.
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I chose it because it was a useful module and had mostly clean coding. It requires only 5 pins and about 5% of a Nexys2 fpga.The following changes were made:
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1) Stripped off the bus interface.
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You never want to create a component and then hard wire it to any particular bus interface. Create the core engine with documentation and test suite.
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Then you can create another component that instantiates the core along with the bus of the day interface. If the bus registers are created by a tool
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it will be easy to retarget it to any bus the tool supports
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2) Split out each module into a seperate file with replaceable module names and variants
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There were two variations defined for this component. You can now have two instanciations and use both in a single design
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3) Removed the spartan 3 clock gen and ported in pixel_clock and reset
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By receiving the clock and reset from a port this code can now go into any fpga or asic design.
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4) Replaced the char rom with a cde_sram and moved the font into a sw directory
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The font is now compiled from an asm file and loaded with a readmemh command. This enables the support of a ascii only font that is 1/2 the size of the full one.
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5) Replaced the char ram with a cde_ram.
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You can now define a starup screen in a asm file
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6) Connected all signals to instances by name rather than by position
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7) cleaned up port width mismatch,latches and undefined memory accesses
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8) converted from async to sync reset
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9) Combined port i/o and wire/reg declarations
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10) Changed configurations and magic numbers into parameters
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11) Added a simplier color mode for more depth and less per character control
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If you need all the bells and blinking characters you can add it on the outside.
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12) Inverted h+v sync siganals. Not sure which way is rigth by my other one is active low and it works
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13) added test suite with vga_model and micro bus host
