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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [logic/] [ip/] [vga_char_ctrl/] [rtl/] [verilog/] [svga_timing_generation] - Blame information for rev 131

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Line No. Rev Author Line
1 131 jt_eaton
 
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//---------------------------------------------------
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module `VARIANT`SVGA_TIMING_GENERATION
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#(parameter CHARACTER_DECODE_DELAY=4,
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  parameter H_ACTIVE=640,
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  parameter H_FRONT_PORCH=16,
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  parameter H_SYNCH=96,
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  parameter H_BACK_PORCH=48,
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  parameter H_TOTAL=800,
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  parameter V_ACTIVE=480,
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  parameter V_FRONT_PORCH=11,
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  parameter V_SYNCH=2,
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  parameter V_BACK_PORCH=31,
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  parameter V_TOTAL=524
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)
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(
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input                clk,          // pixel clock
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input                reset,        // reset
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output reg           h_synch,      // horizontal synch for VGA connector
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output reg           v_synch,      // vertical synch for VGA connector
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output reg           blank,        // composite blanking
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output reg [10:0]    pixel_count,  // counts the pixels in a line
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output reg [9:0]     line_count,   // counts the display lines
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output reg [2:0]     subchar_pixel,// pixel position within the character
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output reg [2:0]     subchar_line, // identifies the line number within a character block
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output reg [6:0]     char_column,  // character number on the current line
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output reg [6:0]     char_line     // line number on the screen
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 );
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reg                    h_blank;                         // horizontal blanking
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reg                    v_blank;                         // vertical blanking
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reg [9:0]           char_column_count;     // a counter used to define the character column number
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reg [9:0]           char_line_count;          // a counter used to define the character line number
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reg                     reset_char_line;           // flag to reset the character line during VBI
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reg                    reset_char_column;     // flag to reset the character column during HBI
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// CREATE THE HORIZONTAL LINE PIXEL COUNTER
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always @ (posedge clk) begin
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     if (reset)
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          // on reset set pixel counter to 0
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          pixel_count <= 11'd0;
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     else if (pixel_count == (H_TOTAL - 1))
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          // last pixel in the line, so reset pixel counter
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          pixel_count <= 11'd0;
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     else
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          pixel_count <= pixel_count + 1;
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end
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// CREATE THE HORIZONTAL SYNCH PULSE
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always @ (posedge clk ) begin
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     if (reset)
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          // on reset remove h_synch
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          h_synch <= 1'b0;
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     else if (pixel_count == (H_ACTIVE + H_FRONT_PORCH - 1))
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          // start of h_synch
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          h_synch <= 1'b1;
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     else if (pixel_count == (H_TOTAL - H_BACK_PORCH - 1))
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          // end of h_synch
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          h_synch <= 1'b0;
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end
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// CREATE THE VERTICAL FRAME LINE COUNTER
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always @ (posedge clk ) begin
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     if (reset)
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          // on reset set line counter to 0
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          line_count <= 10'd0;
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     else if ((line_count == (V_TOTAL - 1)) & (pixel_count == (H_TOTAL - 1)))
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          // last pixel in last line of frame, so reset line counter
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          line_count <= 10'd0;
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     else if ((pixel_count == (H_TOTAL - 1)))
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          // last pixel but not last line, so increment line counter
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          line_count <= line_count + 1;
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end
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// CREATE THE VERTICAL SYNCH PULSE
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always @ (posedge clk ) begin
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     if (reset)
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          // on reset remove v_synch
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          v_synch <= 1'b0;
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     else if ((line_count == (V_ACTIVE + V_FRONT_PORCH - 1) &
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             (pixel_count == H_TOTAL - 1)))
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          // start of v_synch
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          v_synch <= 1'b1;
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     else if ((line_count == (V_TOTAL - V_BACK_PORCH - 1)) &
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             (pixel_count == (H_TOTAL - 1)))
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          // end of v_synch
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          v_synch <= 1'b0;
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end
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// CREATE THE HORIZONTAL BLANKING SIGNAL
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// the "-2" is used instead of "-1" because of the extra register delay
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// for the composite blanking signal
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always @ (posedge clk ) begin
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     if (reset)
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          // on reset remove the h_blank
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          h_blank <= 1'b0;
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     else if (pixel_count == (H_ACTIVE -2))
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          // start of HBI
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          h_blank <= 1'b1;
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     else if (pixel_count == (H_TOTAL -2))
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          // end of HBI
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          h_blank <= 1'b0;
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end
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// CREATE THE VERTICAL BLANKING SIGNAL
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// the "-2" is used instead of "-1"  in the horizontal factor because of the extra
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// register delay for the composite blanking signal
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always @ (posedge clk ) begin
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     if (reset)
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          // on reset remove v_blank
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          v_blank <= 1'b0;
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     else if ((line_count == (V_ACTIVE - 1) &
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             (pixel_count ==  H_TOTAL - 2)))
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          // start of VBI
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          v_blank <= 1'b1;
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     else if ((line_count == (V_TOTAL - 1)) &
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             (pixel_count == (H_TOTAL - 2)))
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          // end of VBI
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          v_blank <= 1'b0;
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end
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// CREATE THE COMPOSITE BANKING SIGNAL
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always @ (posedge clk ) begin
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     if (reset)
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          // on reset remove blank
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          blank <= 1'b0;
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     // blank during HBI or VBI
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     else if (h_blank || v_blank)
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          blank <= 1'b1;
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     else
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          // active video do not blank
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          blank <= 1'b0;
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end
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/*
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   CREATE THE CHARACTER COUNTER.
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   CHARACTERS ARE DEFINED WITHIN AN 8 x 8 PIXEL BLOCK.
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     A 640  x 480 video mode will display 80  characters on 60 lines.
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     A 800  x 600 video mode will display 100 characters on 75 lines.
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     A 1024 x 768 video mode will display 128 characters on 96 lines.
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     "subchar_line" identifies the row in the 8 x 8 block.
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     "subchar_pixel" identifies the column in the 8 x 8 block.
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*/
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// CREATE THE VERTICAL FRAME LINE COUNTER
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always @ (posedge clk ) begin
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     if (reset)
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           // on reset set line counter to 0
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          subchar_line <= 3'b000;
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     else if  ((line_count == (V_TOTAL - 1)) & (pixel_count == (H_TOTAL - 1) - CHARACTER_DECODE_DELAY))
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          // reset line counter
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          subchar_line <= 3'b000;
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     else if (pixel_count == (H_TOTAL - 1) - CHARACTER_DECODE_DELAY)
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          // increment line counter
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          subchar_line <= line_count[2:0] + 3'b001;
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end
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// subchar_pixel defines the pixel within the character line
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always @ (posedge clk ) begin
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     if (reset)
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          // reset to 5 so that the first character data can be latched
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          subchar_pixel <= 3'b101;
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     else if (pixel_count == ((H_TOTAL - 1) - CHARACTER_DECODE_DELAY))
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          // reset to 5 so that the first character data can be latched
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          subchar_pixel <= 3'b101;
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     else
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          subchar_pixel <= subchar_pixel + 1;
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end
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wire [9:0] char_column_count_iter = char_column_count + 1;
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always @ (posedge clk ) begin
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     if (reset) begin
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          char_column_count <= 10'd0;
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          char_column <= 7'd0;
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     end
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     else if (reset_char_column) begin
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          // reset the char column count during the HBI
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          char_column_count <= 10'd0;
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          char_column <= 7'd0;
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     end
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     else begin
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          char_column_count <= char_column_count_iter;
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          char_column <= char_column_count_iter[9:3];
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     end
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end
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wire [9:0] char_line_count_iter = char_line_count + 1;
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always @ (posedge clk ) begin
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     if (reset) begin
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          char_line_count <= 10'd0;
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          char_line <= 7'd0;
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     end
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     else if (reset_char_line) begin
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          // reset the char line count during the VBI
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          char_line_count <= 10'd0;
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          char_line <= 7'd0;
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     end
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     else if (pixel_count == ((H_TOTAL - 1) - CHARACTER_DECODE_DELAY)) begin
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          // last pixel but not last line, so increment line counter
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          char_line_count <= char_line_count_iter;
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          char_line <= char_line_count_iter[9:3];
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     end
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end
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// CREATE THE CONTROL SIGNALS FOR THE CHARACTER ADDRESS COUNTERS
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/*
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     The HOLD and RESET signals are advanced from the beginning and end
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     of HBI and VBI to compensate for the internal character generation
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     pipeline.
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*/
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always @ (posedge clk ) begin
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     if (reset)
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          reset_char_column <= 1'b0;
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     else if (pixel_count == ((H_ACTIVE - 2) - CHARACTER_DECODE_DELAY))
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          // start of HBI
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          reset_char_column <= 1'b1;
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     else if (pixel_count == ((H_TOTAL - 1) - CHARACTER_DECODE_DELAY))
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           // end of HBI
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          reset_char_column <= 1'b0;
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end
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always @ (posedge clk ) begin
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     if (reset)
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          reset_char_line <= 1'b0;
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     else if ((line_count == (V_ACTIVE - 1)) &
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             (pixel_count == ((H_ACTIVE - 1) - CHARACTER_DECODE_DELAY)))
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          // start of VBI
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          reset_char_line <= 1'b1;
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     else if ((line_count == (V_TOTAL - 1)) &
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             (pixel_count == ((H_TOTAL - 1) - CHARACTER_DECODE_DELAY)))
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          // end of VBI
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          reset_char_line <= 1'b0;
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end
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endmodule //SVGA_TIMING_GENERATION
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