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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [logic/] [ip/] [vga_char_ctrl/] [rtl/] [verilog/] [top.body] - Blame information for rev 131

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Line No. Rev Author Line
1 131 jt_eaton
//----------------------------------------------------------------------------
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// user_logic.v - module
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//----------------------------------------------------------------------------
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//
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//  This program is free software: you can redistribute it and/or modify
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//  it under the terms of the GNU General Public License as published by
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//  the Free Software Foundation, either version 3 of the License, or
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//  (at your option) any later version.
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//
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//  This program is distributed in the hope that it will be useful,
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//  but WITHOUT ANY WARRANTY; without even the implied warranty of
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//  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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//  GNU General Public License for more details.
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//
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//  You should have received a copy of the GNU General Public License
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//  along with this program.  If not, see .
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//
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//----------------------------------------------------------------------------
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wire pixel_on;
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wire h_synch;
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wire v_synch;
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wire blank;
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// instantiate the character generator
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`VARIANT`CHAR_DISPLAY
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#(.H_ACTIVE(H_ACTIVE))
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 CHAR_DISPLAY
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  (
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  .clk               ( clk           ),
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  .reset             ( reset         ),
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  .char_column       ( char_column   ),
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  .char_line         ( char_line     ),
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  .subchar_line      ( subchar_line  ),
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  .subchar_pixel     ( subchar_pixel ),
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  .pixel_on          ( pixel_on      ),
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  .char_read_addr    ( char_read_addr),
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  .char_write_addr   ( address       ),
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  .char_write_data   ( wdata         ),
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  .char_write_enable ( ascii_load    ),
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  .ascii_code        ( ascii_code    )
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);
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// instantiate the video timing generator
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`VARIANT`SVGA_TIMING_GENERATION
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 #(.CHARACTER_DECODE_DELAY(CHARACTER_DECODE_DELAY),
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   .H_ACTIVE(H_ACTIVE),
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   .H_FRONT_PORCH(H_FRONT_PORCH),
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   .H_SYNCH(H_SYNCH),
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   .H_BACK_PORCH(H_BACK_PORCH),
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   .H_TOTAL(H_TOTAL),
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   .V_ACTIVE(V_ACTIVE),
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   .V_FRONT_PORCH(V_FRONT_PORCH),
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   .V_SYNCH(V_SYNCH),
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   .V_BACK_PORCH(V_BACK_PORCH),
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   .V_TOTAL(V_TOTAL)
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  )
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 SVGA_TIMING_GENERATION
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(
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  .clk            ( clk          ),
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  .reset          ( reset        ),
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  .h_synch        ( h_synch      ),
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  .v_synch        ( v_synch      ),
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  .blank          ( blank        ),
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  .pixel_count    ( pixel_count  ),
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  .line_count     ( line_count   ),
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  .subchar_pixel  ( subchar_pixel),
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  .subchar_line   ( subchar_line ),
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  .char_column    ( char_column  ),
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  .char_line      ( char_line    )
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);
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// instantiate the video output mux
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`VARIANT`VIDEO_OUT
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 VIDEO_OUT
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(
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  .clk                ( clk             ),
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  .reset              ( reset           ),
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  .h_synch            ( h_synch         ),
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  .v_synch            ( v_synch         ),
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  .blank              ( blank           ),
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  .char_color         ( char_color      ),
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  .back_color         ( back_color      ),
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  .cursor_color       ( cursor_color    ),
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  .pixel_on           ( pixel_on        ),
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  .cursor_on          ( cursor_on       ),
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  .hsync_n_out        ( hsync_n_pad_out ),
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  .vsync_n_out        ( vsync_n_pad_out ),
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  .red_out            ( red_pad_out     ),
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  .green_out          ( green_pad_out   ),
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  .blue_out           ( blue_pad_out    )
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);
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always @ (posedge clk )
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   if (reset)    cursor_on <=  1'b0;
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   else          cursor_on <= (char_read_addr ==  address) ;
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always@(posedge clk)
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  if(reset)       address <= 14'b00000000000000;
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  else
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  if(add_l_load)  address[7:0] <= wdata;
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  else
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  if(add_h_load)  address[13:8] <= wdata[5:0];
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  else
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  if(ascii_load)  address  <= address+ 14'b0000000000001;
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  else            address  <= address;
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