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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [logic/] [ip/] [vga_char_ctrl/] [rtl/] [verilog/] [video_out] - Blame information for rev 131

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module `VARIANT`VIDEO_OUT
(
 
 
input   wire        clk,
input   wire        reset,
input   wire        h_synch,
input   wire        v_synch,
input   wire        blank,
input   wire        pixel_on,
input   wire        cursor_on,
 
input   wire [7:0]  char_color,
input   wire [7:0]  cursor_color,
input   wire [7:0]  back_color,
 
output   reg        hsync_n_out,
output   reg        vsync_n_out,
output   reg  [2:0] red_out,
output   reg  [2:0] green_out,
output   reg  [1:0] blue_out
 
 );
 
 
 
 
 
// make the external video connections
always @ (posedge clk ) begin
     if (reset) begin
          // shut down the video output during reset
          hsync_n_out                <= 1'b1;
          vsync_n_out                <= 1'b1;
     end
 
     else begin
          // output color data otherwise
          hsync_n_out                <= !h_synch;
          vsync_n_out                <= !v_synch;
     end
end
 
 
 
 
 
// make the external video connections
always @ (posedge clk )
     begin
     if (reset)
        begin
        // shut down the video output during reset
        red_out     <=    3'b000;
        green_out   <=    3'b000;
        blue_out    <=    2'b00;
        end
 
     else
     if (blank)
        begin
        // output black during the blank signal
        red_out     <=    3'b000;
        green_out   <=    3'b000;
        blue_out    <=    2'b00;
        end
 
     else
     if (cursor_on)
        begin
        // output black during the blank signal
        red_out     <=    cursor_color[7:5];
        green_out   <=    cursor_color[4:2];
        blue_out    <=    cursor_color[1:0];
        end
 
     else
     if (pixel_on)
        begin
        // output black during the blank signal
        red_out     <=    char_color[7:5];
        green_out   <=    char_color[4:2];
        blue_out    <=    char_color[1:0];
        end
     else
        begin
        // output black during the blank signal
        red_out     <=    back_color[7:5];
        green_out   <=    back_color[4:2];
        blue_out    <=    back_color[1:0];
        end
     end
 
 
 
 
endmodule // VIDEO_OUT

Line No.	Rev	Author	Line
1	131	jt_eaton	module `VARIANT`VIDEO_OUT
2			`(`
3
4
5			`input wire clk,`
6			`input wire reset,`
7			`input wire h_synch,`
8			`input wire v_synch,`
9			`input wire blank,`
10			`input wire pixel_on,`
11			`input wire cursor_on,`
12
13			`input wire [7:0] char_color,`
14			`input wire [7:0] cursor_color,`
15			`input wire [7:0] back_color,`
16
17			`output reg hsync_n_out,`
18			`output reg vsync_n_out,`
19			`output reg [2:0] red_out,`
20			`output reg [2:0] green_out,`
21			`output reg [1:0] blue_out`
22
23			`);`
24
25
26
27
28
29			`// make the external video connections`
30			`always @ (posedge clk ) begin`
31			`if (reset) begin`
32			`// shut down the video output during reset`
33			`hsync_n_out <= 1'b1;`
34			`vsync_n_out <= 1'b1;`
35			`end`
36
37			`else begin`
38			`// output color data otherwise`
39			`hsync_n_out <= !h_synch;`
40			`vsync_n_out <= !v_synch;`
41			`end`
42			`end`
43
44
45
46
47
48			`// make the external video connections`
49			`always @ (posedge clk )`
50			`begin`
51			`if (reset)`
52			`begin`
53			`// shut down the video output during reset`
54			`red_out <= 3'b000;`
55			`green_out <= 3'b000;`
56			`blue_out <= 2'b00;`
57			`end`
58
59			`else`
60			`if (blank)`
61			`begin`
62			`// output black during the blank signal`
63			`red_out <= 3'b000;`
64			`green_out <= 3'b000;`
65			`blue_out <= 2'b00;`
66			`end`
67
68			`else`
69			`if (cursor_on)`
70			`begin`
71			`// output black during the blank signal`
72			`red_out <= cursor_color[7:5];`
73			`green_out <= cursor_color[4:2];`
74			`blue_out <= cursor_color[1:0];`
75			`end`
76
77			`else`
78			`if (pixel_on)`
79			`begin`
80			`// output black during the blank signal`
81			`red_out <= char_color[7:5];`
82			`green_out <= char_color[4:2];`
83			`blue_out <= char_color[1:0];`
84			`end`
85			`else`
86			`begin`
87			`// output black during the blank signal`
88			`red_out <= back_color[7:5];`
89			`green_out <= back_color[4:2];`
90			`blue_out <= back_color[1:0];`
91			`end`
92			`end`
93
94
95
96
97			`endmodule // VIDEO_OUT`

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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [logic/] [ip/] [vga_char_ctrl/] [rtl/] [verilog/] [video_out] - Blame information for rev 131