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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [logic/] [ip/] [vga_char_ctrl/] [rtl/] [xml/] [vga_char_ctrl_def.xml] - Blame information for rev 131

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xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
 
opencores.org
logic
vga_char_ctrl
def  default
 
 
 

 
 slave_clk
  
  
  
    
      
        clk
        clk
      
    
 
 
 
 slave_reset
  
  
  
    
      
        reset
        reset
      
    
 
 
 
 
 
 
 vga
  
  
  
    
 
      
        hsync_n_pad_out
        hsync_n_pad_out
      
 
      
        vsync_n_pad_out
        vsync_n_pad_out
      
 
 
      
        red_pad_out
        
        red_pad_out
          20
        
      
 
 
      
        green_pad_out
        
        green_pad_out
          20
        
      
 
 
      
        blue_pad_out
        
        blue_pad_out
          10
        
      
 
 
    
 
 
 
 
 
 
 
 
 
 
 

 
 
 

 
 
 
 
 
 
 

  gen_verilog
  104.0
  none
  common
  ./tools/verilog/gen_verilog
    
    
      destination
      top
    
    
      dest_dir
      ../verilog
    
  

 
 
 
 
 

 
 
 
  
 
    
      fs-common
 
      
        
        ../verilog/top.body
        verilogSourcefragment
      
 
 
    
 
 
    
      fs-sim
 
      
        
        ../verilog/copyright.v
        verilogSourceinclude
      
 
      
        
        ../verilog/common/top
        verilogSourcemodule
      
 
      
        char_display
        ../verilog/char_display
        verilogSourcemodule
      
 
      
        char_gen
        ../verilog/char_gen
        verilogSourcemodule
      
 
      
        svga_timing_generation
        ../verilog/svga_timing_generation
        verilogSourcemodule
      
 
      
        video_out
        ../verilog/video_out
        verilogSourcemodule
      
 
 
 
    
 
 
    
      fs-syn
 
 
      
        
        ../verilog/copyright.v
        verilogSourceinclude
      
 
      
        
        ../verilog/common/top
        verilogSourcemodule
      
 
      
        char_display
        ../verilog/char_display
        verilogSourcemodule
      
 
      
        char_gen
        ../verilog/char_gen
        verilogSourcemodule
      
 
      
        svga_timing_generation
        ../verilog/svga_timing_generation
        verilogSourcemodule
      
 
      
        video_out
        ../verilog/video_out
        verilogSourcemodule
      
 
 
 
    
 
 
 
 
 
 
  
 
 
 
 

       
 
              
              Hierarchical
 
              
                                   spirit:library="logic"
                                   spirit:name="vga_char_ctrl"
                                   spirit:version="def.design"/>
              
 
              
              verilog
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="verilog"/>
              
              
 
 
 
 
 
 
              
              commoncommon
              Verilog
              
                     
                            fs-common
                     
              
 
 
              
              sim:*Simulation:*
              Verilog
              
                     
                            fs-sim
                     
              
 
 
              
              syn:*Synthesis:*
              Verilog
              
                     
                            fs-syn
                     
              
 
 
              
              doc
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="documentation"/>
              
              :*Documentation:*
              Verilog
              
 
 
      
 
 
 

CHARACTER_DECODE_DELAY4
H_ACTIVE640
H_FRONT_PORCH16
H_SYNCH96
H_BACK_PORCH48
H_TOTAL800
V_ACTIVE480
V_FRONT_PORCH11
V_SYNCH2
V_BACK_PORCH31
V_TOTAL524

 

 
 
ascii_load
wire
in

 
add_l_load
wire
in

 
add_h_load
wire
in

 
wdata
wire
in
70

 
address
reg
out
130

 
char_color
wire
in
70

 
back_color
wire
in
70

 
cursor_color
wire
in
70

 
 
 
 
 

 

 
 
 
 
 


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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [logic/] [ip/] [vga_char_ctrl/] [rtl/] [xml/] [vga_char_ctrl_def.xml] - Blame information for rev 131

Line No.	Rev	Author	Line
1	131	jt_eaton
2
30
31			`xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"`
32			`xmlns:socgen="http://opencores.org"`
33			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
34			`xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009`
35			`http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">`
36
37			`opencores.org`
38			`logic`
39			`vga_char_ctrl`
40			`def default`
41
42
43
44
45
46			`slave_clk`
47
48
49
50
51
52			`clk`
53			`clk`
54
55
56
57
58
59			`slave_reset`
60
61
62
63
64
65			`reset`
66			`reset`
67
68
69
70
71
72
73
74
75			`vga`
76
77
78
79
80
81
82			`hsync_n_pad_out`
83			`hsync_n_pad_out`
84
85
86
87			`vsync_n_pad_out`
88			`vsync_n_pad_out`
89
90
91
92
93			`red_pad_out`
94
95			`red_pad_out`
96			`20`
97
98
99
100
101
102			`green_pad_out`
103
104			`green_pad_out`
105			`20`
106
107
108
109
110
111			`blue_pad_out`
112
113			`blue_pad_out`
114			`10`
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144			`gen_verilog`
145			`104.0`
146			`none`
147			`common`
148			`./tools/verilog/gen_verilog`
149
150
151			`destination`
152			`top`
153
154
155			`dest_dir`
156			`../verilog`
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172			`fs-common`
173
174
175
176			`../verilog/top.body`
177			`verilogSourcefragment`
178
179
180
181
182
183
184
185			`fs-sim`
186
187
188
189			`../verilog/copyright.v`
190			`verilogSourceinclude`
191
192
193
194
195			`../verilog/common/top`
196			`verilogSourcemodule`
197
198
199
200			`char_display`
201			`../verilog/char_display`
202			`verilogSourcemodule`
203
204
205
206			`char_gen`
207			`../verilog/char_gen`
208			`verilogSourcemodule`
209
210
211
212			`svga_timing_generation`
213			`../verilog/svga_timing_generation`
214			`verilogSourcemodule`
215
216
217
218			`video_out`
219			`../verilog/video_out`
220			`verilogSourcemodule`
221
222
223
224
225
226
227
228
229			`fs-syn`
230
231
232
233
234			`../verilog/copyright.v`
235			`verilogSourceinclude`
236
237
238
239
240			`../verilog/common/top`
241			`verilogSourcemodule`
242
243
244
245			`char_display`
246			`../verilog/char_display`
247			`verilogSourcemodule`
248
249
250
251			`char_gen`
252			`../verilog/char_gen`
253			`verilogSourcemodule`
254
255
256
257			`svga_timing_generation`
258			`../verilog/svga_timing_generation`
259			`verilogSourcemodule`
260
261
262
263			`video_out`
264			`../verilog/video_out`
265			`verilogSourcemodule`
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286			`Hierarchical`
287
288
289			`spirit:library="logic"`
290			`spirit:name="vga_char_ctrl"`
291			`spirit:version="def.design"/>`
292
293
294
295			`verilog`
296
297
298			`spirit:library="Testbench"`
299			`spirit:name="toolflow"`
300			`spirit:version="verilog"/>`
301
302
303
304
305
306
307
308
309
310			`commoncommon`
311			`Verilog`
312
313
314			`fs-common`
315
316
317
318
319
320			`sim:Simulation:`
321			`Verilog`
322
323
324			`fs-sim`
325
326
327
328
329
330			`syn:Synthesis:`
331			`Verilog`
332
333
334			`fs-syn`
335
336
337
338
339
340			`doc`
341
342
343			`spirit:library="Testbench"`
344			`spirit:name="toolflow"`
345			`spirit:version="documentation"/>`
346
347			`:Documentation:`
348			`Verilog`
349
350
351
352
353
354
355
356
357			`CHARACTER_DECODE_DELAY4`
358			`H_ACTIVE640`
359			`H_FRONT_PORCH16`
360			`H_SYNCH96`
361			`H_BACK_PORCH48`
362			`H_TOTAL800`
363			`V_ACTIVE480`
364			`V_FRONT_PORCH11`
365			`V_SYNCH2`
366			`V_BACK_PORCH31`
367			`V_TOTAL524`
368
369
370
371
372
373			`ascii_load`
374			`wire`
375			`in`
376
377
378			`add_l_load`
379			`wire`
380			`in`
381
382
383			`add_h_load`
384			`wire`
385			`in`
386
387
388			`wdata`
389			`wire`
390			`in`
391			`70`
392
393
394			`address`
395			`reg`
396			`out`
397			`130`
398
399
400			`char_color`
401			`wire`
402			`in`
403			`70`
404
405
406			`back_color`
407			`wire`
408			`in`
409			`70`
410
411
412			`cursor_color`
413			`wire`
414			`in`
415			`70`
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430