Subversion Repositories socgen

xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"

xmlns:socgen="http://opencores.org"

xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"

xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009

http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">

opencores.org

logic

vga_char_ctrl

def  default

 slave_clk

        clk

        clk

 slave_reset

        reset

        reset

 vga

        hsync_n_pad_out

        hsync_n_pad_out

        vsync_n_pad_out

        vsync_n_pad_out

        red_pad_out

        red_pad_out

          20

        green_pad_out

        green_pad_out

          20

        blue_pad_out

        blue_pad_out

          10

  elab_verilog

  102.1

  none

  :*Simulation:*

  ./tools/verilog/elab_verilog

      dest_dir

      io_ports

  gen_verilog

  104.0

  none

  common

  ./tools/verilog/gen_verilog

      destination

      top

      dest_dir

      ../verilog

      fs-common

        ../verilog/top.body

        verilogSourcefragment

      fs-sim

        ../verilog/copyright.v

        verilogSourceinclude

        ../verilog/common/top

        verilogSourcemodule

        char_display

        ../verilog/char_display

        verilogSourcemodule

        char_gen

        ../verilog/char_gen

        verilogSourcemodule

        svga_timing_generation

        ../verilog/svga_timing_generation

        verilogSourcemodule

        video_out

        ../verilog/video_out

        verilogSourcemodule

      fs-syn

        ../verilog/copyright.v

        verilogSourceinclude

        ../verilog/common/top

        verilogSourcemodule

        char_display

        ../verilog/char_display

        verilogSourcemodule

        char_gen

        ../verilog/char_gen

        verilogSourcemodule

        svga_timing_generation

        ../verilog/svga_timing_generation

        verilogSourcemodule

        video_out

        ../verilog/video_out

        verilogSourcemodule

              Hierarchical

                                   spirit:library="logic"

                                   spirit:name="vga_char_ctrl"

                                   spirit:version="def.design"/>

              verilog

                                   spirit:library="Testbench"

                                   spirit:name="toolflow"

                                   spirit:version="verilog"/>

              commoncommon

              Verilog

                            fs-common

              sim:*Simulation:*

              Verilog

                            fs-sim

              syn:*Synthesis:*

              Verilog

                            fs-syn

              doc

                                   spirit:library="Testbench"

                                   spirit:name="toolflow"

                                   spirit:version="documentation"/>

              :*Documentation:*

              Verilog

CHARACTER_DECODE_DELAY4

H_ACTIVE640

H_FRONT_PORCH16

H_SYNCH96

H_BACK_PORCH48

H_TOTAL800

V_ACTIVE480

V_FRONT_PORCH11

V_SYNCH2

V_BACK_PORCH31

V_TOTAL524

CHAR_RAM_ADDR13

CHAR_RAM_WIDTH8

CHAR_RAM_WORDS4800

CHAR_RAM_WRITETHRU0

CHAR_RAM_DEFAULT8'hff

ascii_load

wire

in

add_l_load

wire

in

add_h_load

wire

in

wdata

wire

in

70

address

reg

out

130

char_color

wire

in

70

back_color

wire

in

70

cursor_color

wire

in

70