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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [wishbone/] [busDefs/] [abstractors/] [wb_b.3_rtl.xml] - Blame information for rev 135

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xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014
http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">
 
opencores.org
wishbone
wb
b.3_rtl
 

  
 
   
      clk
      The clock input coordinates all activities for the internal logic within the WISHBONE interconnect. All WISHBONE output signals are registered at the rising edge of clk. All WISHBONE input signals are stable before the rising edge of clk.
      
        
          true
        
        
          CLOCK
          required
          1
          out
        
        
          RESET
          optional
          1
          out
        
        
          required
          1
          in
        
        
          required
          1
          in
        
        true
      
    
 
    
      enable
      The enable input determines if a clk cycle should be acted upon or ignored for all operations including reset.
      
        
          CLOCK
          illegal
        
        
          ENABLE
          required
          1
          out
        
        
          optional
          1
          in
        
        
          optional
          1
          in
        
      
    
 
 
    
      rst
      The rst input forces the WISHBONE interface to restart. Furthermore, all internal self-starting state machines will be forced into an initial state. This signal only resets the WISHBONE interface. It is not required to reset other parts of an IP core (although it may be used that way).
      
        
          true
        
        
          CLOCK
          illegal
        
        
          ENABLE
          illegal
        
        
          RESET
          required
          1
          out
        
        
          required
          1
          in
        
        
          required
          1
          in
        
        true
      
    
 
 
 
    
      adr
      The adr output array is used to pass a binary address. The higher array boundary is specific to the address width of the core, and the lower array boundary is determined by the data port size and granularity. For example the array size on a 32-bit data port with BYTE granularity is adr[n:2]. In some cases (such as FIFO interfaces) the array may not be present on the interface.
      
        
          true
        
        
          CLOCK
          illegal
        
        
          ENABLE
          illegal
        
        
          RESET
          illegal
        
        
          required
          out
        
        
          required
          in
        
      
    
 
 
 
    
      cyc
      The cycle output when asserted, indicates that a valid bus cycle is in progress. The signal is asserted for the duration of all bus cycles. For example, during a BLOCK transfer cycle there can be multiple data transfers. The signal is asserted during the first data transfer, and remains asserted until the last data transfer. The signal is useful for interfaces with multi-port interfaces (such as dual port memories). In these cases, the  signal requests use of a common bus from an arbiter.
      
        
          true
        
        
          CLOCK
          illegal
        
        
          ENABLE
          illegal
        
        
          RESET
          illegal
        
        
          required
          out
        
        
          required
          in
        
      
    
 
 
 
 
 
    
      wdata
      The data output array is used to pass binary data. The array boundaries are determined by the port size, with a maximum port size of 64-bits (e.g. wdata[63:0].Also see the rdata[] and sel[] signal descriptions.
      
        
          CLOCK
          illegal
        
        
          ENABLE
          illegal
        
        
          RESET
          illegal
        
        
          required
          out
        
        
          required
          in
        
      
    
 
    
      rdata
      The data input array is used to pass binary data. The array boundaries are determined by the port size, with a maximum port size of 64-bits (e.g. rdata[63:0]. Also see the wdata[] and sel[] signal descriptions.
      
        
          CLOCK
          illegal
        
        
          ENABLE
          illegal
        
        
          RESET
          illegal
        
        
          required
          in
        
        
          required
          out
        
      
    
 
 
   
      ack
      The acknowledge input  when asserted, indicates the normal termination of a bus cycle. Also see the err and rty signal descriptions.
      
        
          CLOCK
          illegal
        
        
          ENABLE
          illegal
        
        
          RESET
          illegal
        
        
          required
          in
        
        
          required
          out
        
      
    
 
 
   
      err
      The error input indicates an abnormal cycle termination. The source of the error, and the response generated by the MASTER is defined by the IP core supplier. Also see the ack and rty signal descriptions.
      
        
          CLOCK
          illegal
        
        
          ENABLE
          illegal
        
        
          RESET
          illegal
        
        
          required
          in
        
        
          required
          out
        
      
    
 
 
   
      rty
      The retry input indicates that the interface is not ready to accept or send data, and that the cycle should be retried. When and how the cycle is retried is defined by the IP core supplier. Also see the ack and err signal descriptions.
      
        
          CLOCK
          illegal
        
        
          ENABLE
          illegal
        
        
          RESET
          illegal
        
        
          required
          in
        
        
          required
          out
        
      
    
 
 
 
   
      stall
      The pipeline stall input indicates that current slave is not able to accept the transfer in the transaction queue. This signal is used in pipelined mode.
      
        
          CLOCK
          illegal
        
        
          ENABLE
          illegal
        
        
          RESET
          illegal
        
        
          required
          in
        
        
          required
          out
        
      
    
 
 
 
 
 
   
      lock
      The lock output when asserted, indicates that the current bus cycle is uninterruptible. Lock is asserted to request complete ownership of the bus. Once the transfer has started, the INTERCON does not grant the bus to any other MASTER, until the current MASTER negates lock or cyc.
      
        
          CLOCK
          illegal
        
        
          ENABLE
          illegal
        
        
          RESET
          illegal
        
        
          required
          out
        
        
          required
          in
        
      
    
 
 
 
 
 
   
      sel
      The select output array indicates where valid data is expected on the rdata signal array during READ cycles, and where it is placed on the wdata signal array during WRITE cycles. The array boundaries are determined by the granularity of a port. For example, if 8-bit granularity is used on a 64-bit port, then there would be an array of eight select signals with boundaries of sel[7:0]. Each individual select signal correlates to one of eight active bytes on the 64-bit data port. For more information about sel, please refer to the data organization section in Chapter 3 of this specification. Also see the rdata[], wdata[] and stb signal descriptions.
      
        
          CLOCK
          illegal
        
        
          ENABLE
          illegal
        
        
          RESET
          illegal
        
        
          required
          out
        
        
          required
          in
        
      
    
 
 
 
 
   
      stb
      The strobe output indicates a valid data transfer cycle. It is used to qualify various other signals on the interface such as sel[]. The SLAVE asserts either the ack, err  or rty signals in response to every assertion of the stb signal.
      
        
          CLOCK
          illegal
        
        
          ENABLE
          illegal
        
        
          RESET
          illegal
        
        
          required
          out
        
        
          required
          in
        
      
    
 
 
   
      wtgd
      Data tag type is used on MASTER and SLAVE interfaces. It contains information that is associated with the data input array wdata[], and is qualified by signal stb. For example, parity protection, error correction and time stamp information can be attached to the data bus. These tag bits simplify the task of defining new signals because their timing (in relation to every bus cycle) is pre-defined by this specification. The name and operation of a data tag must be defined in the WISHBONE DATASHEET.
      
        
          CLOCK
          illegal
        
        
          ENABLE
          illegal
        
        
          RESET
          illegal
        
        
          required
          out
        
        
          required
          in
        
      
    
 
 
 
 
   
      rtgd
      Data tag type is used on MASTER and SLAVE interfaces. It contains information that is associated with the data output array rdata[], and is qualified by signal stb. For example, parity protection, error correction and time stamp information can be attached to the data bus. These tag bits simplify the task of defining new signals because their timing (in relation to every bus cycle) is pre-defined by this specification. The name and operation of a data tag must be defined in the WISHBONE DATASHEET.
      
        
          CLOCK
          illegal
        
        
          ENABLE
          illegal
        
        
          RESET
          illegal
        
        
          required
          in
        
        
          required
          out
        
      
    
 
 
 
 
    
      tga
      Address tag type contains information associated with address lines adr[], and is qualified by signal stb. For example, address size (24-bit, 32-bit etc.) and memory management (protected vs. unprotected) information can be attached to an address. These tag bits simplify the task of defining new signals because their timing (in relation to every bus cycle) is defined by this specification. The name and operation of an address tag must be defined in the WISHBONE DATASHEET.
      
        
          true
        
        
          CLOCK
          illegal
        
        
          ENABLE
          illegal
        
        
          RESET
          illegal
        
        
          required
          out
        
        
          required
          in
        
      
    
 
 
 
    
      tgc
      Cycle tag type  contains information associated with bus cycles, and is qualified by signal cyc. For example, data transfer, interrupt acknowledge and cache control cycles can be uniquely identified with the cycle tag. They can also be used to discriminate between WISHBONE SINGLE, BLOCK and RMW cycles. These tag bits simplify the task of defining new signals because their timing (in relation to every bus cycle) is defined by this specification. The name and operation of a cycle tag must be defined in the WISHBONE DATASHEET.
      
        
          true
        
        
          CLOCK
          illegal
        
        
          ENABLE
          illegal
        
        
          RESET
          illegal
        
        
          required
          out
        
        
          required
          in
        
      
    
 
 
 
    
      we
      The write enable output indicates whether the current local bus cycle is a READ or WRITE cycle. The signal is negated during READ cycles, and is asserted during WRITE cycles.
      
        
          true
        
        
          CLOCK
          illegal
        
        
          ENABLE
          illegal
        
        
          RESET
          illegal
        
        
          required
          out
        
        
          required
          in
        
      
    
 
 
 
 
  

 
 
 
 
 
 
 
 
 

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Subversion Repositories socgen

[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [wishbone/] [busDefs/] [abstractors/] [wb_b.3_rtl.xml] - Blame information for rev 135

Line No.	Rev	Author	Line
1	131	jt_eaton
2
30
31	135	jt_eaton
32			`xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"`
33	131	jt_eaton	`xmlns:socgen="http://opencores.org"`
34			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
35	135	jt_eaton	`xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014`
36			`http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">`
37	131	jt_eaton
38	135	jt_eaton	`opencores.org`
39			`wishbone`
40			`wb`
41			`b.3_rtl`
42	131	jt_eaton
43	135	jt_eaton
44
45	131	jt_eaton
46	135	jt_eaton
47			`clk`
48			`The clock input coordinates all activities for the internal logic within the WISHBONE interconnect. All WISHBONE output signals are registered at the rising edge of clk. All WISHBONE input signals are stable before the rising edge of clk.`
49
50
51			`true`
52
53
54			`CLOCK`
55			`required`
56			`1`
57			`out`
58
59
60			`RESET`
61			`optional`
62			`1`
63			`out`
64
65
66			`required`
67			`1`
68			`in`
69
70
71			`required`
72			`1`
73			`in`
74
75			`true`
76
77
78	131	jt_eaton
79	135	jt_eaton
80			`enable`
81			`The enable input determines if a clk cycle should be acted upon or ignored for all operations including reset.`
82
83
84			`CLOCK`
85			`illegal`
86
87
88			`ENABLE`
89			`required`
90			`1`
91			`out`
92
93
94			`optional`
95			`1`
96			`in`
97
98
99			`optional`
100			`1`
101			`in`
102
103
104
105	131	jt_eaton
106
107	135	jt_eaton
108			`rst`
109			`The rst input forces the WISHBONE interface to restart. Furthermore, all internal self-starting state machines will be forced into an initial state. This signal only resets the WISHBONE interface. It is not required to reset other parts of an IP core (although it may be used that way).`
110
111
112			`true`
113
114
115			`CLOCK`
116			`illegal`
117
118
119			`ENABLE`
120			`illegal`
121
122
123			`RESET`
124			`required`
125			`1`
126			`out`
127
128
129			`required`
130			`1`
131			`in`
132
133
134			`required`
135			`1`
136			`in`
137
138			`true`
139
140
141	131	jt_eaton
142
143
144	135	jt_eaton
145			`adr`
146			`The adr output array is used to pass a binary address. The higher array boundary is specific to the address width of the core, and the lower array boundary is determined by the data port size and granularity. For example the array size on a 32-bit data port with BYTE granularity is adr[n:2]. In some cases (such as FIFO interfaces) the array may not be present on the interface.`
147
148
149			`true`
150
151
152			`CLOCK`
153			`illegal`
154
155
156			`ENABLE`
157			`illegal`
158
159
160			`RESET`
161			`illegal`
162
163
164			`required`
165			`out`
166
167
168			`required`
169			`in`
170
171
172
173	131	jt_eaton
174
175
176	135	jt_eaton
177			`cyc`
178			`The cycle output when asserted, indicates that a valid bus cycle is in progress. The signal is asserted for the duration of all bus cycles. For example, during a BLOCK transfer cycle there can be multiple data transfers. The signal is asserted during the first data transfer, and remains asserted until the last data transfer. The signal is useful for interfaces with multi-port interfaces (such as dual port memories). In these cases, the signal requests use of a common bus from an arbiter.`
179
180
181			`true`
182
183
184			`CLOCK`
185			`illegal`
186
187
188			`ENABLE`
189			`illegal`
190
191
192			`RESET`
193			`illegal`
194
195
196			`required`
197			`out`
198
199
200			`required`
201			`in`
202
203
204
205	131	jt_eaton
206
207
208
209
210	135	jt_eaton
211			`wdata`
212			`The data output array is used to pass binary data. The array boundaries are determined by the port size, with a maximum port size of 64-bits (e.g. wdata[63:0].Also see the rdata[] and sel[] signal descriptions.`
213
214
215			`CLOCK`
216			`illegal`
217
218
219			`ENABLE`
220			`illegal`
221
222
223			`RESET`
224			`illegal`
225
226
227			`required`
228			`out`
229
230
231			`required`
232			`in`
233
234
235
236	131	jt_eaton
237	135	jt_eaton
238			`rdata`
239			`The data input array is used to pass binary data. The array boundaries are determined by the port size, with a maximum port size of 64-bits (e.g. rdata[63:0]. Also see the wdata[] and sel[] signal descriptions.`
240
241
242			`CLOCK`
243			`illegal`
244
245
246			`ENABLE`
247			`illegal`
248
249
250			`RESET`
251			`illegal`
252
253
254			`required`
255			`in`
256
257
258			`required`
259			`out`
260
261
262
263	131	jt_eaton
264
265	135	jt_eaton
266			`ack`
267			`The acknowledge input when asserted, indicates the normal termination of a bus cycle. Also see the err and rty signal descriptions.`
268
269
270			`CLOCK`
271			`illegal`
272
273
274			`ENABLE`
275			`illegal`
276
277
278			`RESET`
279			`illegal`
280
281
282			`required`
283			`in`
284
285
286			`required`
287			`out`
288
289
290
291	131	jt_eaton
292
293	135	jt_eaton
294			`err`
295			`The error input indicates an abnormal cycle termination. The source of the error, and the response generated by the MASTER is defined by the IP core supplier. Also see the ack and rty signal descriptions.`
296
297
298			`CLOCK`
299			`illegal`
300
301
302			`ENABLE`
303			`illegal`
304
305
306			`RESET`
307			`illegal`
308
309
310			`required`
311			`in`
312
313
314			`required`
315			`out`
316
317
318
319	131	jt_eaton
320
321	135	jt_eaton
322			`rty`
323			`The retry input indicates that the interface is not ready to accept or send data, and that the cycle should be retried. When and how the cycle is retried is defined by the IP core supplier. Also see the ack and err signal descriptions.`
324
325
326			`CLOCK`
327			`illegal`
328
329
330			`ENABLE`
331			`illegal`
332
333
334			`RESET`
335			`illegal`
336
337
338			`required`
339			`in`
340
341
342			`required`
343			`out`
344
345
346
347	131	jt_eaton
348
349
350	135	jt_eaton
351			`stall`
352			`The pipeline stall input indicates that current slave is not able to accept the transfer in the transaction queue. This signal is used in pipelined mode.`
353
354
355			`CLOCK`
356			`illegal`
357
358
359			`ENABLE`
360			`illegal`
361
362
363			`RESET`
364			`illegal`
365
366
367			`required`
368			`in`
369
370
371			`required`
372			`out`
373
374
375
376	131	jt_eaton
377
378
379
380
381	135	jt_eaton
382			`lock`
383			`The lock output when asserted, indicates that the current bus cycle is uninterruptible. Lock is asserted to request complete ownership of the bus. Once the transfer has started, the INTERCON does not grant the bus to any other MASTER, until the current MASTER negates lock or cyc.`
384
385
386			`CLOCK`
387			`illegal`
388
389
390			`ENABLE`
391			`illegal`
392
393
394			`RESET`
395			`illegal`
396
397
398			`required`
399			`out`
400
401
402			`required`
403			`in`
404
405
406
407	131	jt_eaton
408
409
410
411
412	135	jt_eaton
413			`sel`
414			The select output array indicates where valid data is expected on the rdata signal array during READ cycles, and where it is placed on the wdata signal array during WRITE cycles. The array boundaries are determined by the granularity of a port. For example, if 8-bit granularity is used on a 64-bit port, then there would be an array of eight select signals with boundaries of sel[7:0]. Each individual select signal correlates to one of eight active bytes on the 64-bit data port. For more information about sel, please refer to the data organization section in Chapter 3 of this specification. Also see the rdata[], wdata[] and stb signal descriptions.
415
416
417			`CLOCK`
418			`illegal`
419
420
421			`ENABLE`
422			`illegal`
423
424
425			`RESET`
426			`illegal`
427
428
429			`required`
430			`out`
431
432
433			`required`
434			`in`
435
436
437
438	131	jt_eaton
439
440
441
442	135	jt_eaton
443			`stb`
444			`The strobe output indicates a valid data transfer cycle. It is used to qualify various other signals on the interface such as sel[]. The SLAVE asserts either the ack, err or rty signals in response to every assertion of the stb signal.`
445
446
447			`CLOCK`
448			`illegal`
449
450
451			`ENABLE`
452			`illegal`
453
454
455			`RESET`
456			`illegal`
457
458
459			`required`
460			`out`
461
462
463			`required`
464			`in`
465
466
467
468	131	jt_eaton
469
470	135	jt_eaton
471			`wtgd`
472			Data tag type is used on MASTER and SLAVE interfaces. It contains information that is associated with the data input array wdata[], and is qualified by signal stb. For example, parity protection, error correction and time stamp information can be attached to the data bus. These tag bits simplify the task of defining new signals because their timing (in relation to every bus cycle) is pre-defined by this specification. The name and operation of a data tag must be defined in the WISHBONE DATASHEET.
473
474
475			`CLOCK`
476			`illegal`
477
478
479			`ENABLE`
480			`illegal`
481
482
483			`RESET`
484			`illegal`
485
486
487			`required`
488			`out`
489
490
491			`required`
492			`in`
493
494
495
496	131	jt_eaton
497
498
499
500	135	jt_eaton
501			`rtgd`
502			Data tag type is used on MASTER and SLAVE interfaces. It contains information that is associated with the data output array rdata[], and is qualified by signal stb. For example, parity protection, error correction and time stamp information can be attached to the data bus. These tag bits simplify the task of defining new signals because their timing (in relation to every bus cycle) is pre-defined by this specification. The name and operation of a data tag must be defined in the WISHBONE DATASHEET.
503
504
505			`CLOCK`
506			`illegal`
507
508
509			`ENABLE`
510			`illegal`
511
512
513			`RESET`
514			`illegal`
515
516
517			`required`
518			`in`
519
520
521			`required`
522			`out`
523
524
525
526	131	jt_eaton
527
528
529
530	135	jt_eaton
531			`tga`
532			`Address tag type contains information associated with address lines adr[], and is qualified by signal stb. For example, address size (24-bit, 32-bit etc.) and memory management (protected vs. unprotected) information can be attached to an address. These tag bits simplify the task of defining new signals because their timing (in relation to every bus cycle) is defined by this specification. The name and operation of an address tag must be defined in the WISHBONE DATASHEET.`
533
534
535			`true`
536
537
538			`CLOCK`
539			`illegal`
540
541
542			`ENABLE`
543			`illegal`
544
545
546			`RESET`
547			`illegal`
548
549
550			`required`
551			`out`
552
553
554			`required`
555			`in`
556
557
558
559	131	jt_eaton
560
561
562	135	jt_eaton
563			`tgc`
564			Cycle tag type contains information associated with bus cycles, and is qualified by signal cyc. For example, data transfer, interrupt acknowledge and cache control cycles can be uniquely identified with the cycle tag. They can also be used to discriminate between WISHBONE SINGLE, BLOCK and RMW cycles. These tag bits simplify the task of defining new signals because their timing (in relation to every bus cycle) is defined by this specification. The name and operation of a cycle tag must be defined in the WISHBONE DATASHEET.
565
566
567			`true`
568
569
570			`CLOCK`
571			`illegal`
572
573
574			`ENABLE`
575			`illegal`
576
577
578			`RESET`
579			`illegal`
580
581
582			`required`
583			`out`
584
585
586			`required`
587			`in`
588
589
590
591	131	jt_eaton
592
593
594	135	jt_eaton
595			`we`
596			`The write enable output indicates whether the current local bus cycle is a READ or WRITE cycle. The signal is negated during READ cycles, and is asserted during WRITE cycles.`
597
598
599			`true`
600
601
602			`CLOCK`
603			`illegal`
604
605
606			`ENABLE`
607			`illegal`
608
609
610			`RESET`
611			`illegal`
612
613
614			`required`
615			`out`
616
617
618			`required`
619			`in`
620
621
622
623	131	jt_eaton
624
625
626
627	135	jt_eaton
628
629	131	jt_eaton
630
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