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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [wishbone/] [busDefs/] [abstractors/] [wishbone_rtl.xml] - Blame information for rev 135

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xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"
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xmlns:socgen="http://opencores.org"
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xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
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xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014
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http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">
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opencores.org
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wishbone
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wishbone
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rtl
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      clk
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      The bus clock times all bus transfers. All signal timings are related to the rising edge
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          true
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          CLOCK
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          optional
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          1
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          RESET
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          illegal
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          CLOCKEN
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          illegal
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        true
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        0
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      reset_n
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      The reset_n signal is asynchronous active LOW.
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          true
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          CLOCK
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          illegal
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          RESET
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          optional
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          1
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          CLOCKEN
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          illegal
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        true
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        0
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      reset
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      The reset signal is synchronous active HIGH.
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          CLOCK
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          illegal
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          RESET
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          optional
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          1
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          CLOCKEN
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          illegal
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        1
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      clk_en
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      The clk_en signal is active HIGH.
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          CLOCK
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          illegal
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          RESET
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          illegal
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          CLOCKEN
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          optional
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          1
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        1
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      wdata
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          out
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          in
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      rdata
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          in
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          out
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      wtgd
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          out
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          in
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      rtgd
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          in
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          out
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      ack
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          in
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      adr
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          out
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          in
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      cyc
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          out
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          in
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      stall
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          in
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      cab
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          in
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      err
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          in
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      lock
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          in
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      rty
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          in
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      sel
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          in
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      stb
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          in
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      tga
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      tgc
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      cti
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      bte
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      we
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