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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [wishbone/] [doc/] [Heda/] [absDef/] [wishbone_rtl.txt] - Blame information for rev 131

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opencores.org:wishbone:wishbone:rtl
        --------------------------------------------------------------------------------------------------------
        Filename:  ./projects/opencores.org/wishbone/busDefs/abstractors/wishbone_rtl.xml
        VLNV-ad     opencores.org_wishbone_wishbone_rtl
        VLNV-bt     opencores.org_wishbone_wishbone_def
             SystemGroup Name CLOCK
             SystemGroup Name RESET
             SystemGroup Name CLOCKEN
 
Port:  clk   CLOCK  Requires Driver  clock
 
Port:  reset_n   RESET  Requires Driver  singleShot
 
Port:  reset       Default Value   1
 
Port:  clk_en       Default Value   1
 
Port:  wdata
 
Port:  rdata
 
Port:  wtgd
 
Port:  rtgd
 
Port:  ack
 
Port:  adr
 
Port:  cyc
 
Port:  stall
 
Port:  cab
 
Port:  err
 
Port:  lock
 
Port:  rty
 
Port:  sel
 
Port:  stb
 
Port:  tga
 
Port:  tgc
 
Port:  cti
 
Port:  bte
 
Port:  we
 

Line No.	Rev	Author	Line
1	131	jt_eaton	`opencores.org:wishbone:wishbone:rtl`
2			`--------------------------------------------------------------------------------------------------------`
3			`Filename: ./projects/opencores.org/wishbone/busDefs/abstractors/wishbone_rtl.xml`
4			`VLNV-ad opencores.org_wishbone_wishbone_rtl`
5			`VLNV-bt opencores.org_wishbone_wishbone_def`
6			`SystemGroup Name CLOCK`
7			`SystemGroup Name RESET`
8			`SystemGroup Name CLOCKEN`
9
10			`Port: clk CLOCK Requires Driver clock`
11
12			`Port: reset_n RESET Requires Driver singleShot`
13
14			`Port: reset Default Value 1`
15
16			`Port: clk_en Default Value 1`
17
18			`Port: wdata`
19
20			`Port: rdata`
21
22			`Port: wtgd`
23
24			`Port: rtgd`
25
26			`Port: ack`
27
28			`Port: adr`
29
30			`Port: cyc`
31
32			`Port: stall`
33
34			`Port: cab`
35
36			`Port: err`
37
38			`Port: lock`
39
40			`Port: rty`
41
42			`Port: sel`
43
44			`Port: stb`
45
46			`Port: tga`
47
48			`Port: tgc`
49
50			`Port: cti`
51
52			`Port: bte`
53
54			`Port: we`
55

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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [wishbone/] [doc/] [Heda/] [absDef/] [wishbone_rtl.txt] - Blame information for rev 131