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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [wishbone/] [ip/] [model/] [rtl/] [xml/] [model_master.xml] - Blame information for rev 131

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xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
 
opencores.org
wishbone
model
master  default
 
 
 

 
 
wb
   
   
   
     
 
        
         adr
         
         adr
           wb_addr_width-10
         
       
 
 
        
         wdata
         
         dout
           wb_data_width-10
         
       
 
 
        
         rdata
         
         din
           wb_data_width-10
         
       
 
 
        
         sel
         
         sel
         
       
 
 
        
         ack
         
         ack
         
       
 
 
        
         cyc
         
         cyc
         
       
 
 
 
        
         stb
         
         stb
         
       
 
 
        
         we
         
         we
         
       
 
 
 
 
 
 
 
     
 

 

 
 
 
 
 
 
 
 
  
 
 
    
      fs-sim
 
      
        dest_dir../verilog/sim/
        verilogSourcelibraryDir
      
 
    
 
    
      fs-syn
 
 
      
        dest_dir../verilog/syn/
        verilogSourcelibraryDir
      
 
 
    
 
 
  
 
 
 
 
 

 
 
 
 

dwidth32
awidth32

 

 
clk
wire
in

 
reset
wire
in

 
adr
reg
out
awidth-10

 
 
dout
reg
out
dwidth0

 
 
cyc
reg
out

 
stb
reg
out

 
we
reg
out

 
 
sel
reg
out
dwidth/8-10

 
 
din
wire
in
dwidth-10

 
 
ack
wire
in

 
err
wire
in

 
rty
wire
in

 
 

 

 
 
 
 
 
 
 
 


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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [wishbone/] [ip/] [model/] [rtl/] [xml/] [model_master.xml] - Blame information for rev 131

Line No.	Rev	Author	Line
1	131	jt_eaton
2
30
31			`xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"`
32			`xmlns:socgen="http://opencores.org"`
33			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
34			`xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009`
35			`http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">`
36
37			`opencores.org`
38			`wishbone`
39			`model`
40			`master default`
41
42
43
44
45
46
47			`wb`
48
49
50
51
52
53
54			`adr`
55
56			`adr`
57			`wb_addr_width-10`
58
59
60
61
62
63			`wdata`
64
65			`dout`
66			`wb_data_width-10`
67
68
69
70
71
72			`rdata`
73
74			`din`
75			`wb_data_width-10`
76
77
78
79
80
81			`sel`
82
83			`sel`
84
85
86
87
88
89			`ack`
90
91			`ack`
92
93
94
95
96
97			`cyc`
98
99			`cyc`
100
101
102
103
104
105
106			`stb`
107
108			`stb`
109
110
111
112
113
114			`we`
115
116			`we`
117
118
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120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
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142
143			`fs-sim`
144
145
146			`dest_dir../verilog/sim/`
147			`verilogSourcelibraryDir`
148
149
150
151
152
153			`fs-syn`
154
155
156
157			`dest_dir../verilog/syn/`
158			`verilogSourcelibraryDir`
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177			`dwidth32`
178			`awidth32`
179
180
181
182
183			`clk`
184			`wire`
185			`in`
186
187
188			`reset`
189			`wire`
190			`in`
191
192
193			`adr`
194			`reg`
195			`out`
196			`awidth-10`
197
198
199
200			`dout`
201			`reg`
202			`out`
203			`dwidth0`
204
205
206
207			`cyc`
208			`reg`
209			`out`
210
211
212			`stb`
213			`reg`
214			`out`
215
216
217			`we`
218			`reg`
219			`out`
220
221
222
223			`sel`
224			`reg`
225			`out`
226			`dwidth/8-10`
227
228
229
230			`din`
231			`wire`
232			`in`
233			`dwidth-10`
234
235
236
237			`ack`
238			`wire`
239			`in`
240
241
242			`err`
243			`wire`
244			`in`
245
246
247			`rty`
248			`wire`
249			`in`
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264