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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [wishbone/] [ip/] [model/] [rtl/] [xml/] [model_monitor.xml] - Blame information for rev 131

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xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
 
opencores.org
wishbone
model
monitor  default
 
 
 
 
 
 
 
 
 
  
 
 
    
      fs-sim
 
      
        dest_dir../verilog/sim/
        verilogSourcelibraryDir
      
 
 
 
 
    
 
 
    
      fs-syn
 
 
      
        dest_dir../verilog/syn/
        verilogSourcelibraryDir
      
 
 
    
 
 
 
  
 
 
 
 
 
 

 
 
 

TEST_NAME"unspecified"
INSTANCE"none"
ADD_WIDTH32
DATA_WIDTH32

 

 
clk
wire
in

 
reset
wire
in

 
wb_adr
wire
in
ADD_WIDTH-10

 
wb_ack
wire
in

 
wb_err
wire
in

 
wb_cyc
wire
in

 
wb_stb
wire
in

 
wb_we
wire
in

 
 
wb_read
wire
in
DATA_WIDTH-10

 
wb_write
wire
in
DATA_WIDTH-10

 
 
wb_sel
wire
in
30

 

 

 
 
 
 
 
 
 
 
 
 


Line No.	Rev	Author	Line
1	131	jt_eaton
2
30
31			`xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"`
32			`xmlns:socgen="http://opencores.org"`
33			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
34			`xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009`
35			`http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">`
36
37			`opencores.org`
38			`wishbone`
39			`model`
40			`monitor default`
41
42
43
44
45
46
47
48
49
50
51
52
53
54			`fs-sim`
55
56
57			`dest_dir../verilog/sim/`
58			`verilogSourcelibraryDir`
59
60
61
62
63
64
65
66
67
68			`fs-syn`
69
70
71
72			`dest_dir../verilog/syn/`
73			`verilogSourcelibraryDir`
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
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91
92
93			`TEST_NAME"unspecified"`
94			`INSTANCE"none"`
95			`ADD_WIDTH32`
96			`DATA_WIDTH32`
97
98
99
100
101			`clk`
102			`wire`
103			`in`
104
105
106			`reset`
107			`wire`
108			`in`
109
110
111			`wb_adr`
112			`wire`
113			`in`
114			`ADD_WIDTH-10`
115
116
117			`wb_ack`
118			`wire`
119			`in`
120
121
122			`wb_err`
123			`wire`
124			`in`
125
126
127			`wb_cyc`
128			`wire`
129			`in`
130
131
132			`wb_stb`
133			`wire`
134			`in`
135
136
137			`wb_we`
138			`wire`
139			`in`
140
141
142
143			`wb_read`
144			`wire`
145			`in`
146			`DATA_WIDTH-10`
147
148
149			`wb_write`
150			`wire`
151			`in`
152			`DATA_WIDTH-10`
153
154
155
156			`wb_sel`
157			`wire`
158			`in`
159			`30`
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175

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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [wishbone/] [ip/] [model/] [rtl/] [xml/] [model_monitor.xml] - Blame information for rev 131