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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [wishbone/] [ip/] [wb_memory/] [sim/] [icarus/] [default/] [test_define] - Blame information for rev 131

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Line No. Rev Author Line
1 131 jt_eaton
 
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reg [31:0] d;
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initial
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 begin
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 $display("              ");
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 $display("          ===================================================");
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 $display("%t  Test Start",$realtime  );
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 $display("          ===================================================");
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 $display("              ");
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 test.cg.next(8);
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 test.cg.next(88);
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 $display("%t  Out of reset  ",$realtime  );
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 test.i_wb_master.wb_write( 20'h00000,4'b0001, 32'h00000012);
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 test.i_wb_master.wb_write( 20'h00000,4'b0010, 32'h00003400);
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 test.i_wb_master.wb_write( 20'h00000,4'b0100, 32'h00560000);
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 test.i_wb_master.wb_write( 20'h00000,4'b1000, 32'h78000000);
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 test.cg.next(8);
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 test.i_wb_master.wb_write( 20'h00040,4'b1111, 32'h5a);
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 test.cg.next(8);
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 test.i_wb_master.wb_write( 20'h00080,4'b1111, 32'h208);
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 test.cg.next(8);
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 test.i_wb_master.wb_write( 20'h000c0,4'b1111, 32'h01);
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 test.i_wb_master.wb_read( 20'h00000, d);
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 test.cg.next(8);
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 test.i_wb_master.wb_read( 20'h00040, d);
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 test.cg.next(8);
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 test.i_wb_master.wb_read( 20'h00080, d);
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 test.cg.next(8);
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 test.i_wb_master.wb_read( 20'h000c0, d);
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 test.cg.next(8);
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 $display("%t verified registers", $realtime);
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 test.i_wb_master.wb_cmp( 20'h00000,4'b1111, 32'h78563412 );
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 test.cg.next(8);
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 test.i_wb_master.wb_cmp( 20'h00040,4'b1111, 32'h5a );
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 test.cg.next(8);
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 test.i_wb_master.wb_cmp( 20'h00080,4'b1111, 32'h208 );
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 test.cg.next(8);
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 test.i_wb_master.wb_cmp( 20'h000c0,4'b1111, 32'h01 );
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 test.cg.next(8);
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 test.cg.next(100);
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test.cg.exit;
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end
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