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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [wishbone/] [ip/] [wb_memory/] [sim/] [testbenches/] [xml/] [wb_memory_def_tb.xml] - Blame information for rev 131

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xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
 
opencores.org
wishbone
wb_memory
def_tb
 
 
 
 
 
 

 
 
 

  gen_verilog
  104.0
  none
  common
  ./tools/verilog/gen_verilog
    
    
      destination
      top.tb
    
    
      dest_dir
      ../verilog
    
    
      top
    
  

 
 
 

 
 
 
 

 
 
       
 
 
 
              
              Params
              
              
                                   spirit:library="wishbone"
                                   spirit:name="wb_memory"
                                   spirit:version="def_dut.params"/>
             
              
 
              
              Bfm
              
                                   spirit:library="wishbone"
                                   spirit:name="wb_memory"
                                   spirit:version="bfm.design"/>
              
 
 
 
              
              icarus
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="icarus"/>
              
              
 
 
 
 
              
              commoncommon
              Verilog
              
                     
                            fs-common
                     
              
 
 
              
              sim:*Simulation:*
              Verilog
              
                     
                            fs-sim
                     
              
 
              
              lint:*Lint:*
              Verilog
              
                     
                            fs-lint
                     
              
 
      
 
 
 
 
 
 

 
 
 
  
 
    
      fs-common
 
 
      
        
        ../verilog/tb.ext
        verilogSourcefragment
      
 
    
 
 
    
      fs-sim
 
 
      
        
        ../verilog/common/top.tb
        verilogSourcemodule
      
 
 
 
    
 
 
 
 
    
      fs-lint
 
 
      
        
        ../verilog/common/top.tb
        verilogSourcemodule
      
 
 
    
 
 
 
 
  
 
 
 
 

 
 

Line No.	Rev	Author	Line
1	131	jt_eaton
2
30
31			`xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"`
32			`xmlns:socgen="http://opencores.org"`
33			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
34			`xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009`
35			`http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">`
36
37			`opencores.org`
38			`wishbone`
39			`wb_memory`
40			`def_tb`
41
42
43
44
45
46
47
48
49
50
51
52			`gen_verilog`
53			`104.0`
54			`none`
55			`common`
56			`./tools/verilog/gen_verilog`
57
58
59			`destination`
60			`top.tb`
61
62
63			`dest_dir`
64			`../verilog`
65
66
67			`top`
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87			`Params`
88
89
90			`spirit:library="wishbone"`
91			`spirit:name="wb_memory"`
92			`spirit:version="def_dut.params"/>`
93
94
95
96
97			`Bfm`
98
99			`spirit:library="wishbone"`
100			`spirit:name="wb_memory"`
101			`spirit:version="bfm.design"/>`
102
103
104
105
106
107			`icarus`
108
109
110			`spirit:library="Testbench"`
111			`spirit:name="toolflow"`
112			`spirit:version="icarus"/>`
113
114
115
116
117
118
119
120			`commoncommon`
121			`Verilog`
122
123
124			`fs-common`
125
126
127
128
129
130			`sim:Simulation:`
131			`Verilog`
132
133
134			`fs-sim`
135
136
137
138
139			`lint:Lint:`
140			`Verilog`
141
142
143			`fs-lint`
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161			`fs-common`
162
163
164
165
166			`../verilog/tb.ext`
167			`verilogSourcefragment`
168
169
170
171
172
173
174			`fs-sim`
175
176
177
178
179			`../verilog/common/top.tb`
180			`verilogSourcemodule`
181
182
183
184
185
186
187
188
189
190
191			`fs-lint`
192
193
194
195
196			`../verilog/common/top.tb`
197			`verilogSourcemodule`
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
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Subversion Repositories socgen

[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [wishbone/] [ip/] [wb_memory/] [sim/] [testbenches/] [xml/] [wb_memory_def_tb.xml] - Blame information for rev 131