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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [wishbone/] [ip/] [wb_model/] [rtl/] [xml/] [wb_model_master.xml] - Blame information for rev 131

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xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
 
opencores.org
wishbone
wb_model
master  default
 
 
 

 
 
wb
   
   
   
     
 
        
         adr
         
         adr
           wb_addr_width-10
         
       
 
 
        
         wdata
         
         dout
           wb_data_width-10
         
       
 
 
        
         rdata
         
         din
           wb_data_width-10
         
       
 
 
        
         sel
         
         sel
         
       
 
 
        
         ack
         
         ack
         
       
 
 
        
         cyc
         
         cyc
         
       
 
 
 
        
         stb
         
         stb
         
       
 
 
        
         we
         
         we
         
       
 
 
 
 
 
 
 
     
 

 

 
 
 
 
 
 

 

  gen_verilogLib_sim
  105.0
  none
  :*Simulation:*
  ./tools/verilog/gen_verilogLib
    
    
      dest_dir
      ../views
    
  
    
      view
      sim
    

 
 

  gen_verilogLib_syn
  105.0
  none
  :*Synthesis:*
  ./tools/verilog/gen_verilogLib
    
    
      dest_dir
      ../views
    
  
    
      view
      syn
    

 
 
 
 

 
 
 
 
  
 
 
    
      fs-sim
 
      
        
        ../verilog/copyright.v
        verilogSourceinclude
      
 
      
        
        ../verilog/top.sim
        verilogSourcemodule
      
 
    
 
    
      fs-syn
 
      
        
        ../verilog/copyright.v
        verilogSourceinclude
      
 
      
        
        ../verilog/top.syn
        verilogSourcemodule
      
 
      
        dest_dir../views/syn/
        verilogSourcelibraryDir
      
 
 
    
 
 
  
 
 
 
 
 

       
 
 
              
              sim:*Simulation:*
 
              Verilog
              
                     
                            fs-sim
                     
              
 
              
              syn:*Synthesis:*
 
              Verilog
              
                     
                            fs-syn
                     
              
 
 
              
              doc
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="documentation"/>
              
              :*Documentation:*
              Verilog
              
 
      
 
 
 

dwidth32
awidth32

 

 
clk
wire
in

 
reset
wire
in

 
adr
reg
out
awidth-10

 
 
dout
reg
out
dwidth0

 
 
cyc
reg
out

 
stb
reg
out

 
we
reg
out

 
 
sel
reg
out
dwidth/8-10

 
 
din
wire
in
dwidth-10

 
 
ack
wire
in

 
err
wire
in

 
rty
wire
in

 
 

 

 
 
 
 
 
 
 
 


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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [wishbone/] [ip/] [wb_model/] [rtl/] [xml/] [wb_model_master.xml] - Blame information for rev 131

Line No.	Rev	Author	Line
1	131	jt_eaton
2
30
31			`xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"`
32			`xmlns:socgen="http://opencores.org"`
33			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
34			`xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009`
35			`http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">`
36
37			`opencores.org`
38			`wishbone`
39			`wb_model`
40			`master default`
41
42
43
44
45
46
47			`wb`
48
49
50
51
52
53
54			`adr`
55
56			`adr`
57			`wb_addr_width-10`
58
59
60
61
62
63			`wdata`
64
65			`dout`
66			`wb_data_width-10`
67
68
69
70
71
72			`rdata`
73
74			`din`
75			`wb_data_width-10`
76
77
78
79
80
81			`sel`
82
83			`sel`
84
85
86
87
88
89			`ack`
90
91			`ack`
92
93
94
95
96
97			`cyc`
98
99			`cyc`
100
101
102
103
104
105
106			`stb`
107
108			`stb`
109
110
111
112
113
114			`we`
115
116			`we`
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140			`gen_verilogLib_sim`
141			`105.0`
142			`none`
143			`:Simulation:`
144			`./tools/verilog/gen_verilogLib`
145
146
147			`dest_dir`
148			`../views`
149
150
151
152			`view`
153			`sim`
154
155
156
157
158
159			`gen_verilogLib_syn`
160			`105.0`
161			`none`
162			`:Synthesis:`
163			`./tools/verilog/gen_verilogLib`
164
165
166			`dest_dir`
167			`../views`
168
169
170
171			`view`
172			`syn`
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188			`fs-sim`
189
190
191
192			`../verilog/copyright.v`
193			`verilogSourceinclude`
194
195
196
197
198			`../verilog/top.sim`
199			`verilogSourcemodule`
200
201
202
203
204
205			`fs-syn`
206
207
208
209			`../verilog/copyright.v`
210			`verilogSourceinclude`
211
212
213
214
215			`../verilog/top.syn`
216			`verilogSourcemodule`
217
218
219
220			`dest_dir../views/syn/`
221			`verilogSourcelibraryDir`
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239			`sim:Simulation:`
240
241			`Verilog`
242
243
244			`fs-sim`
245
246
247
248
249			`syn:Synthesis:`
250
251			`Verilog`
252
253
254			`fs-syn`
255
256
257
258
259
260			`doc`
261
262
263			`spirit:library="Testbench"`
264			`spirit:name="toolflow"`
265			`spirit:version="documentation"/>`
266
267			`:Documentation:`
268			`Verilog`
269
270
271
272
273
274
275
276			`dwidth32`
277			`awidth32`
278
279
280
281
282			`clk`
283			`wire`
284			`in`
285
286
287			`reset`
288			`wire`
289			`in`
290
291
292			`adr`
293			`reg`
294			`out`
295			`awidth-10`
296
297
298
299			`dout`
300			`reg`
301			`out`
302			`dwidth0`
303
304
305
306			`cyc`
307			`reg`
308			`out`
309
310
311			`stb`
312			`reg`
313			`out`
314
315
316			`we`
317			`reg`
318			`out`
319
320
321
322			`sel`
323			`reg`
324			`out`
325			`dwidth/8-10`
326
327
328
329			`din`
330			`wire`
331			`in`
332			`dwidth-10`
333
334
335
336			`ack`
337			`wire`
338			`in`
339
340
341			`err`
342			`wire`
343			`in`
344
345
346			`rty`
347			`wire`
348			`in`
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363