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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [wishbone/] [ip/] [wb_uart16550/] [rtl/] [xml/] [wb_uart16550_bus16_lit.xml] - Blame information for rev 131

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xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
 
opencores.org
wishbone
wb_uart16550
bus16_lit  default
 
 
 

 
 
 wb_clk
  
  
  
    
      
        clk
        wb_clk_i
      
    
 
 
 
 wb_reset
  
  
  
    
      
        reset
        wb_rst_i
      
    
 
 
 
 
 
wb
   
   
   little
   8
        
     
 
        
         adr
         
         wb_adr_i
           71
         
       
 
 
        
         wdata
         
         wb_dat_i
           150
         
       
 
 
        
         rdata
         
         wb_dat_o
           150
         
       
 
 
        
         sel
         
         wb_sel_i
           10
         
       
 
 
 
        
         ack
         
         wb_ack_o
         
       
 
 
        
         cyc
         
         wb_cyc_i
         
       
 
 
 
        
         stb
         
         wb_stb_i
         
       
 
 
        
         we
         
         wb_we_i
         
       
 
 
 
 
 
     
 

 

 
 
 
 
 
 

 

  gen_registers
  103.0
  none
  common
  ./tools/regtool/gen_registers
    
    
      bus_intf
      wb
    
    
      dest_dir
      ../verilog
    
  

 
 
 
 

  gen_verilog
  104.0
  none
  common
  ./tools/verilog/gen_verilog
   
    
      destination
      top.bus16_lit
    
    
      dest_dir
      ../verilog
    
  

 
 
 
 
 

 
 
  
 
 
    
      fs-common
 
      
        
        ../verilog/top.body
        verilogSourcefragment
      
 
 
 
    
 
 
 
    
      fs-sim
 
      
        
        ../verilog/copyright.v
        verilogSourceinclude
      
 
      
        
        ../verilog/common/top.bus16_lit
        verilogSourcemodule
      
 
 
      
        
        ../verilog/defines
        verilogSourceinclude
      
 
      
        wb
        ../verilog/wb_uart16550_bus16_lit_wb
        verilogSourcemodule
      
 
 
      
        raminfr
        ../verilog/raminfr
        verilogSourcemodule
      
 
      
        receiver
        ../verilog/receiver
        verilogSourcemodule
      
 
      
        regs
        ../verilog/regs
        verilogSourcemodule
      
 
      
        rfifo
        ../verilog/rfifo
        verilogSourcemodule
      
 
      
        sync_flops
        ../verilog/sync_flops
        verilogSourcemodule
      
 
      
        tfifo
        ../verilog/tfifo
        verilogSourcemodule
      
 
      
        transmitter
        ../verilog/transmitter
        verilogSourcemodule
      
 
      
        wb_fsm
        ../verilog/wb_fsm
        verilogSourcemodule
      
 
 
 
    
 
 
    
      fs-syn
 
      
        
        ../verilog/copyright.v
        verilogSourceinclude
      
 
      
        
        ../verilog/common/top.bus16_lit
        verilogSourcemodule
      
 
 
 
 
      
        
        ../verilog/defines
        verilogSourceinclude
      
 
      
        wb
        ../verilog/wb_uart16550_bus16_lit_wb
        verilogSourcemodule
      
 
 
      
        raminfr
        ../verilog/raminfr
        verilogSourcemodule
      
 
      
        receiver
        ../verilog/receiver
        verilogSourcemodule
      
 
      
        regs
        ../verilog/regs
        verilogSourcemodule
      
 
      
        rfifo
        ../verilog/rfifo
        verilogSourcemodule
      
 
      
        sync_flops
        ../verilog/sync_flops
        verilogSourcemodule
      
 
      
        tfifo
        ../verilog/tfifo
        verilogSourcemodule
      
 
      
        transmitter
        ../verilog/transmitter
        verilogSourcemodule
      
 
      
        wb_fsm
        ../verilog/wb_fsm
        verilogSourcemodule
      
 
 
 
 
    
 
 
 
 
  
 
 
 
 
 

       
 
 
              
              verilog
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="verilog"/>
              
              
 
 
 
 
 
              
              commoncommon
 
              Verilog
              
                     
                            fs-common
                     
              
 
              
              sim:*Simulation:*
 
              Verilog
              
                     
                            fs-sim
                     
              
 
              
              syn:*Synthesis:*
 
              Verilog
              
                     
                            fs-syn
                     
              
 
 
              
              doc
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="documentation"/>
              
              :*Documentation:*
              Verilog
              
 
      
 
 
 
 

wb_addr_width8
wb_data_width16
wb_byte_lanes2
PRESCALER_PRESET16'h1234

 
 

 
baud_o
  wire
  out

 
cts_pad_i
  wire
  in

 
dcd_pad_i
  wire
  in

 
dsr_pad_i
  wire
  in

 
dtr_pad_o
  wire
  out

 
int_o
  wire
  out

 
 
ri_pad_i
  wire
  in

 
rts_pad_o
  wire
  out

 
srx_pad_i
  wire
  in

 
stx_pad_o
  wire
  out

 
 
 
 

 

 
 
 

 

8
 wb

 wb
 0x00
 
  
  mb_microbus
  0x100
  16
 
 
 
   rb_dll_reg
   0x0
   8
   read-only
  
 
 
   tr_reg
   0x0
   8
   write-strobe
  
 
 
 
   ie_dlh_reg
   0x1
   8
   read-only
  
 
 
   ie_reg
   0x1
   4
   write-strobe
  
 
 
 
   dll_reg
   0x0
   8
   write-strobe
  
 
 
 
   dlh_reg
   0x1
   8
   write-strobe
  
 
 
 
 
   ii_reg
   0x2
   4
   read-only
  
 
 
   fc_reg
   0x2
   8
   write-only
  
 
 
 
   lc_reg
   0x3
   8
   read-write
  
 
 
   mc_reg
   0x4
   5
   read-write
  
 
 
   ls_reg
   0x5
   8
   read-only
  
 
 
   ms_reg
   0x6
   8
   read-only
  
 
 
   sr_reg
   0x7
   8
   read-write
  
 
 
 
   debug_0_reg
   0x8
   32
   read-only
  
 
 
 
   debug_1_reg
   0xc
   32
   read-only
  
 
 
 
 
 
 
 
 
 
 
  
 
 

 

 
 
 
 


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Subversion Repositories socgen

[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [wishbone/] [ip/] [wb_uart16550/] [rtl/] [xml/] [wb_uart16550_bus16_lit.xml] - Blame information for rev 131

Line No.	Rev	Author	Line
1	131	jt_eaton
2
30
31			`xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"`
32			`xmlns:socgen="http://opencores.org"`
33			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
34			`xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009`
35			`http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">`
36
37			`opencores.org`
38			`wishbone`
39			`wb_uart16550`
40			`bus16_lit default`
41
42
43
44
45
46
47			`wb_clk`
48
49
50
51
52
53			`clk`
54			`wb_clk_i`
55
56
57
58
59
60			`wb_reset`
61
62
63
64
65
66			`reset`
67			`wb_rst_i`
68
69
70
71
72
73
74
75			`wb`
76
77
78			`little`
79			`8`
80
81
82
83
84			`adr`
85
86			`wb_adr_i`
87			`71`
88
89
90
91
92
93			`wdata`
94
95			`wb_dat_i`
96			`150`
97
98
99
100
101
102			`rdata`
103
104			`wb_dat_o`
105			`150`
106
107
108
109
110
111			`sel`
112
113			`wb_sel_i`
114			`10`
115
116
117
118
119
120
121			`ack`
122
123			`wb_ack_o`
124
125
126
127
128
129			`cyc`
130
131			`wb_cyc_i`
132
133
134
135
136
137
138			`stb`
139
140			`wb_stb_i`
141
142
143
144
145
146			`we`
147
148			`wb_we_i`
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170			`gen_registers`
171			`103.0`
172			`none`
173			`common`
174			`./tools/regtool/gen_registers`
175
176
177			`bus_intf`
178			`wb`
179
180
181			`dest_dir`
182			`../verilog`
183
184
185
186
187
188
189
190
191			`gen_verilog`
192			`104.0`
193			`none`
194			`common`
195			`./tools/verilog/gen_verilog`
196
197
198			`destination`
199			`top.bus16_lit`
200
201
202			`dest_dir`
203			`../verilog`
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219			`fs-common`
220
221
222
223			`../verilog/top.body`
224			`verilogSourcefragment`
225
226
227
228
229
230
231
232
233
234			`fs-sim`
235
236
237
238			`../verilog/copyright.v`
239			`verilogSourceinclude`
240
241
242
243
244			`../verilog/common/top.bus16_lit`
245			`verilogSourcemodule`
246
247
248
249
250
251			`../verilog/defines`
252			`verilogSourceinclude`
253
254
255
256			`wb`
257			`../verilog/wb_uart16550_bus16_lit_wb`
258			`verilogSourcemodule`
259
260
261
262
263			`raminfr`
264			`../verilog/raminfr`
265			`verilogSourcemodule`
266
267
268
269			`receiver`
270			`../verilog/receiver`
271			`verilogSourcemodule`
272
273
274
275			`regs`
276			`../verilog/regs`
277			`verilogSourcemodule`
278
279
280
281			`rfifo`
282			`../verilog/rfifo`
283			`verilogSourcemodule`
284
285
286
287			`sync_flops`
288			`../verilog/sync_flops`
289			`verilogSourcemodule`
290
291
292
293			`tfifo`
294			`../verilog/tfifo`
295			`verilogSourcemodule`
296
297
298
299			`transmitter`
300			`../verilog/transmitter`
301			`verilogSourcemodule`
302
303
304
305			`wb_fsm`
306			`../verilog/wb_fsm`
307			`verilogSourcemodule`
308
309
310
311
312
313
314
315
316			`fs-syn`
317
318
319
320			`../verilog/copyright.v`
321			`verilogSourceinclude`
322
323
324
325
326			`../verilog/common/top.bus16_lit`
327			`verilogSourcemodule`
328
329
330
331
332
333
334
335			`../verilog/defines`
336			`verilogSourceinclude`
337
338
339
340			`wb`
341			`../verilog/wb_uart16550_bus16_lit_wb`
342			`verilogSourcemodule`
343
344
345
346
347			`raminfr`
348			`../verilog/raminfr`
349			`verilogSourcemodule`
350
351
352
353			`receiver`
354			`../verilog/receiver`
355			`verilogSourcemodule`
356
357
358
359			`regs`
360			`../verilog/regs`
361			`verilogSourcemodule`
362
363
364
365			`rfifo`
366			`../verilog/rfifo`
367			`verilogSourcemodule`
368
369
370
371			`sync_flops`
372			`../verilog/sync_flops`
373			`verilogSourcemodule`
374
375
376
377			`tfifo`
378			`../verilog/tfifo`
379			`verilogSourcemodule`
380
381
382
383			`transmitter`
384			`../verilog/transmitter`
385			`verilogSourcemodule`
386
387
388
389			`wb_fsm`
390			`../verilog/wb_fsm`
391			`verilogSourcemodule`
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413			`verilog`
414
415
416			`spirit:library="Testbench"`
417			`spirit:name="toolflow"`
418			`spirit:version="verilog"/>`
419
420
421
422
423
424
425
426
427			`commoncommon`
428
429			`Verilog`
430
431
432			`fs-common`
433
434
435
436
437			`sim:Simulation:`
438
439			`Verilog`
440
441
442			`fs-sim`
443
444
445
446
447			`syn:Synthesis:`
448
449			`Verilog`
450
451
452			`fs-syn`
453
454
455
456
457
458			`doc`
459
460
461			`spirit:library="Testbench"`
462			`spirit:name="toolflow"`
463			`spirit:version="documentation"/>`
464
465			`:Documentation:`
466			`Verilog`
467
468
469
470
471
472
473
474
475			`wb_addr_width8`
476			`wb_data_width16`
477			`wb_byte_lanes2`
478			`PRESCALER_PRESET16'h1234`
479
480
481
482
483
484			`baud_o`
485			`wire`
486			`out`
487
488
489			`cts_pad_i`
490			`wire`
491			`in`
492
493
494			`dcd_pad_i`
495			`wire`
496			`in`
497
498
499			`dsr_pad_i`
500			`wire`
501			`in`
502
503
504			`dtr_pad_o`
505			`wire`
506			`out`
507
508
509			`int_o`
510			`wire`
511			`out`
512
513
514
515			`ri_pad_i`
516			`wire`
517			`in`
518
519
520			`rts_pad_o`
521			`wire`
522			`out`
523
524
525			`srx_pad_i`
526			`wire`
527			`in`
528
529
530			`stx_pad_o`
531			`wire`
532			`out`
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547			`8`
548			`wb`
549
550			`wb`
551			`0x00`
552
553
554			`mb_microbus`
555			`0x100`
556			`16`
557
558
559
560			`rb_dll_reg`
561			`0x0`
562			`8`
563			`read-only`
564
565
566
567			`tr_reg`
568			`0x0`
569			`8`
570			`write-strobe`
571
572
573
574
575			`ie_dlh_reg`
576			`0x1`
577			`8`
578			`read-only`
579
580
581
582			`ie_reg`
583			`0x1`
584			`4`
585			`write-strobe`
586
587
588
589
590			`dll_reg`
591			`0x0`
592			`8`
593			`write-strobe`
594
595
596
597
598			`dlh_reg`
599			`0x1`
600			`8`
601			`write-strobe`
602
603
604
605
606
607			`ii_reg`
608			`0x2`
609			`4`
610			`read-only`
611
612
613
614			`fc_reg`
615			`0x2`
616			`8`
617			`write-only`
618
619
620
621
622			`lc_reg`
623			`0x3`
624			`8`
625			`read-write`
626
627
628
629			`mc_reg`
630			`0x4`
631			`5`
632			`read-write`
633
634
635
636			`ls_reg`
637			`0x5`
638			`8`
639			`read-only`
640
641
642
643			`ms_reg`
644			`0x6`
645			`8`
646			`read-only`
647
648
649
650			`sr_reg`
651			`0x7`
652			`8`
653			`read-write`
654
655
656
657
658			`debug_0_reg`
659			`0x8`
660			`32`
661			`read-only`
662
663
664
665
666			`debug_1_reg`
667			`0xc`
668			`32`
669			`read-only`
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691