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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [wishbone/] [ip/] [wb_uart16550/] [rtl/] [xml/] [wb_uart16550_bus16_lit.xml] - Blame information for rev 133

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xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
 
opencores.org
wishbone
wb_uart16550
bus16_lit  default
 
 
 

 
 
 wb_clk
  
  
  
    
      
        clk
        wb_clk_i
      
    
 
 
 
 wb_reset
  
  
  
    
      
        reset
        wb_rst_i
      
    
 
 
 
 
 
wb
   
   
   little
   8
        
     
 
        
         adr
         
         wb_adr_i
           71
         
       
 
 
        
         wdata
         
         wb_dat_i
           150
         
       
 
 
        
         rdata
         
         wb_dat_o
           150
         
       
 
 
        
         sel
         
         wb_sel_i
           10
         
       
 
 
 
        
         ack
         
         wb_ack_o
         
       
 
 
        
         cyc
         
         wb_cyc_i
         
       
 
 
 
        
         stb
         
         wb_stb_i
         
       
 
 
        
         we
         
         wb_we_i
         
       
 
 
 
 
 
     
 

 

 
 
 
 
 
 

 
 

  elab_verilog
  102.1
  none
  :*Simulation:*
  ./tools/verilog/elab_verilog
    
    
      dest_dir
      io_ports
    
  

 
 
 
 

  gen_registers
  102.1
  none
  common
  ./tools/regtool/gen_registers
    
    
      bus_intf
      wb
    
    
      dest_dir
      ../verilog
    
  

 
 
 
 

  gen_verilog
  104.0
  none
  common
  ./tools/verilog/gen_verilog
   
    
      destination
      top.bus16_lit
    
    
      dest_dir
      ../verilog
    
  

 
 
 
 
 

 
 
  
 
 
    
      fs-common
 
      
        
        ../verilog/top.body
        verilogSourcefragment
      
 
 
 
    
 
 
 
    
      fs-sim
 
      
        
        ../verilog/copyright.v
        verilogSourceinclude
      
 
      
        
        ../verilog/common/top.bus16_lit
        verilogSourcemodule
      
 
 
      
        
        ../verilog/defines
        verilogSourceinclude
      
 
      
        wb
        ../verilog/wb_uart16550_bus16_lit_wb
        verilogSourcemodule
      
 
 
      
        raminfr
        ../verilog/raminfr
        verilogSourcemodule
      
 
      
        receiver
        ../verilog/receiver
        verilogSourcemodule
      
 
      
        regs
        ../verilog/regs
        verilogSourcemodule
      
 
      
        rfifo
        ../verilog/rfifo
        verilogSourcemodule
      
 
      
        sync_flops
        ../verilog/sync_flops
        verilogSourcemodule
      
 
      
        tfifo
        ../verilog/tfifo
        verilogSourcemodule
      
 
      
        transmitter
        ../verilog/transmitter
        verilogSourcemodule
      
 
      
        wb_fsm
        ../verilog/wb_fsm
        verilogSourcemodule
      
 
 
 
    
 
 
    
      fs-syn
 
      
        
        ../verilog/copyright.v
        verilogSourceinclude
      
 
      
        
        ../verilog/common/top.bus16_lit
        verilogSourcemodule
      
 
 
 
 
      
        
        ../verilog/defines
        verilogSourceinclude
      
 
      
        wb
        ../verilog/wb_uart16550_bus16_lit_wb
        verilogSourcemodule
      
 
 
      
        raminfr
        ../verilog/raminfr
        verilogSourcemodule
      
 
      
        receiver
        ../verilog/receiver
        verilogSourcemodule
      
 
      
        regs
        ../verilog/regs
        verilogSourcemodule
      
 
      
        rfifo
        ../verilog/rfifo
        verilogSourcemodule
      
 
      
        sync_flops
        ../verilog/sync_flops
        verilogSourcemodule
      
 
      
        tfifo
        ../verilog/tfifo
        verilogSourcemodule
      
 
      
        transmitter
        ../verilog/transmitter
        verilogSourcemodule
      
 
      
        wb_fsm
        ../verilog/wb_fsm
        verilogSourcemodule
      
 
 
 
 
    
 
 
 
 
  
 
 
 
 
 

       
 
 
              
              verilog
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="verilog"/>
              
              
 
 
 
 
 
              
              commoncommon
 
              Verilog
              
                     
                            fs-common
                     
              
 
              
              sim:*Simulation:*
 
              Verilog
              
                     
                            fs-sim
                     
              
 
              
              syn:*Synthesis:*
 
              Verilog
              
                     
                            fs-syn
                     
              
 
 
              
              doc
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="documentation"/>
              
              :*Documentation:*
              Verilog
              
 
      
 
 
 
 

wb_addr_width8
wb_data_width16
wb_byte_lanes2
PRESCALER_PRESET16'h1234

 
 

 
baud_o
  wire
  out

 
cts_pad_i
  wire
  in

 
dcd_pad_i
  wire
  in

 
dsr_pad_i
  wire
  in

 
dtr_pad_o
  wire
  out

 
int_o
  wire
  out

 
 
ri_pad_i
  wire
  in

 
rts_pad_o
  wire
  out

 
srx_pad_i
  wire
  in

 
stx_pad_o
  wire
  out

 
 
 
 

 

 
 
 

 

8
 wb

 wb
 0x00
 
  
  mb_microbus
  0x100
  16
 
 
 
   rb_dll_reg
   0x0
   8
   read-only
  
 
 
   tr_reg
   0x0
   8
   write-strobe
  
 
 
 
   ie_dlh_reg
   0x1
   8
   read-only
  
 
 
   ie_reg
   0x1
   4
   write-strobe
  
 
 
 
   dll_reg
   0x0
   8
   write-strobe
  
 
 
 
   dlh_reg
   0x1
   8
   write-strobe
  
 
 
 
 
   ii_reg
   0x2
   4
   read-only
  
 
 
   fc_reg
   0x2
   8
   write-only
  
 
 
 
   lc_reg
   0x3
   8
   read-write
  
 
 
   mc_reg
   0x4
   5
   read-write
  
 
 
   ls_reg
   0x5
   8
   read-only
  
 
 
   ms_reg
   0x6
   8
   read-only
  
 
 
   sr_reg
   0x7
   8
   read-write
  
 
 
 
   debug_0_reg
   0x8
   32
   read-only
  
 
 
 
   debug_1_reg
   0xc
   32
   read-only
  
 
 
 
 
 
 
 
 
 
 
  
 
 

 

 
 
 
 


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Subversion Repositories socgen

[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [wishbone/] [ip/] [wb_uart16550/] [rtl/] [xml/] [wb_uart16550_bus16_lit.xml] - Blame information for rev 133

Line No.	Rev	Author	Line
1	131	jt_eaton
2
30
31			`xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"`
32			`xmlns:socgen="http://opencores.org"`
33			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
34			`xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009`
35			`http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">`
36
37			`opencores.org`
38			`wishbone`
39			`wb_uart16550`
40			`bus16_lit default`
41
42
43
44
45
46
47			`wb_clk`
48
49
50
51
52
53			`clk`
54			`wb_clk_i`
55
56
57
58
59
60			`wb_reset`
61
62
63
64
65
66			`reset`
67			`wb_rst_i`
68
69
70
71
72
73
74
75			`wb`
76
77
78			`little`
79			`8`
80
81
82
83
84			`adr`
85
86			`wb_adr_i`
87			`71`
88
89
90
91
92
93			`wdata`
94
95			`wb_dat_i`
96			`150`
97
98
99
100
101
102			`rdata`
103
104			`wb_dat_o`
105			`150`
106
107
108
109
110
111			`sel`
112
113			`wb_sel_i`
114			`10`
115
116
117
118
119
120
121			`ack`
122
123			`wb_ack_o`
124
125
126
127
128
129			`cyc`
130
131			`wb_cyc_i`
132
133
134
135
136
137
138			`stb`
139
140			`wb_stb_i`
141
142
143
144
145
146			`we`
147
148			`wb_we_i`
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169	133	jt_eaton
170	131	jt_eaton
171	133	jt_eaton	`elab_verilog`
172			`102.1`
173			`none`
174			`:Simulation:`
175			`./tools/verilog/elab_verilog`
176
177
178			`dest_dir`
179			`io_ports`
180
181
182
183
184
185
186
187
188	131	jt_eaton	`gen_registers`
189	133	jt_eaton	`102.1`
190	131	jt_eaton	`none`
191			`common`
192			`./tools/regtool/gen_registers`
193
194
195			`bus_intf`
196			`wb`
197
198
199			`dest_dir`
200			`../verilog`
201
202
203
204
205
206
207
208
209			`gen_verilog`
210			`104.0`
211			`none`
212			`common`
213			`./tools/verilog/gen_verilog`
214
215
216			`destination`
217			`top.bus16_lit`
218
219
220			`dest_dir`
221			`../verilog`
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237			`fs-common`
238
239
240
241			`../verilog/top.body`
242			`verilogSourcefragment`
243
244
245
246
247
248
249
250
251
252			`fs-sim`
253
254
255
256			`../verilog/copyright.v`
257			`verilogSourceinclude`
258
259
260
261
262			`../verilog/common/top.bus16_lit`
263			`verilogSourcemodule`
264
265
266
267
268
269			`../verilog/defines`
270			`verilogSourceinclude`
271
272
273
274			`wb`
275			`../verilog/wb_uart16550_bus16_lit_wb`
276			`verilogSourcemodule`
277
278
279
280
281			`raminfr`
282			`../verilog/raminfr`
283			`verilogSourcemodule`
284
285
286
287			`receiver`
288			`../verilog/receiver`
289			`verilogSourcemodule`
290
291
292
293			`regs`
294			`../verilog/regs`
295			`verilogSourcemodule`
296
297
298
299			`rfifo`
300			`../verilog/rfifo`
301			`verilogSourcemodule`
302
303
304
305			`sync_flops`
306			`../verilog/sync_flops`
307			`verilogSourcemodule`
308
309
310
311			`tfifo`
312			`../verilog/tfifo`
313			`verilogSourcemodule`
314
315
316
317			`transmitter`
318			`../verilog/transmitter`
319			`verilogSourcemodule`
320
321
322
323			`wb_fsm`
324			`../verilog/wb_fsm`
325			`verilogSourcemodule`
326
327
328
329
330
331
332
333
334			`fs-syn`
335
336
337
338			`../verilog/copyright.v`
339			`verilogSourceinclude`
340
341
342
343
344			`../verilog/common/top.bus16_lit`
345			`verilogSourcemodule`
346
347
348
349
350
351
352
353			`../verilog/defines`
354			`verilogSourceinclude`
355
356
357
358			`wb`
359			`../verilog/wb_uart16550_bus16_lit_wb`
360			`verilogSourcemodule`
361
362
363
364
365			`raminfr`
366			`../verilog/raminfr`
367			`verilogSourcemodule`
368
369
370
371			`receiver`
372			`../verilog/receiver`
373			`verilogSourcemodule`
374
375
376
377			`regs`
378			`../verilog/regs`
379			`verilogSourcemodule`
380
381
382
383			`rfifo`
384			`../verilog/rfifo`
385			`verilogSourcemodule`
386
387
388
389			`sync_flops`
390			`../verilog/sync_flops`
391			`verilogSourcemodule`
392
393
394
395			`tfifo`
396			`../verilog/tfifo`
397			`verilogSourcemodule`
398
399
400
401			`transmitter`
402			`../verilog/transmitter`
403			`verilogSourcemodule`
404
405
406
407			`wb_fsm`
408			`../verilog/wb_fsm`
409			`verilogSourcemodule`
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431			`verilog`
432
433
434			`spirit:library="Testbench"`
435			`spirit:name="toolflow"`
436			`spirit:version="verilog"/>`
437
438
439
440
441
442
443
444
445			`commoncommon`
446
447			`Verilog`
448
449
450			`fs-common`
451
452
453
454
455			`sim:Simulation:`
456
457			`Verilog`
458
459
460			`fs-sim`
461
462
463
464
465			`syn:Synthesis:`
466
467			`Verilog`
468
469
470			`fs-syn`
471
472
473
474
475
476			`doc`
477
478
479			`spirit:library="Testbench"`
480			`spirit:name="toolflow"`
481			`spirit:version="documentation"/>`
482
483			`:Documentation:`
484			`Verilog`
485
486
487
488
489
490
491
492
493			`wb_addr_width8`
494			`wb_data_width16`
495			`wb_byte_lanes2`
496			`PRESCALER_PRESET16'h1234`
497
498
499
500
501
502			`baud_o`
503			`wire`
504			`out`
505
506
507			`cts_pad_i`
508			`wire`
509			`in`
510
511
512			`dcd_pad_i`
513			`wire`
514			`in`
515
516
517			`dsr_pad_i`
518			`wire`
519			`in`
520
521
522			`dtr_pad_o`
523			`wire`
524			`out`
525
526
527			`int_o`
528			`wire`
529			`out`
530
531
532
533			`ri_pad_i`
534			`wire`
535			`in`
536
537
538			`rts_pad_o`
539			`wire`
540			`out`
541
542
543			`srx_pad_i`
544			`wire`
545			`in`
546
547
548			`stx_pad_o`
549			`wire`
550			`out`
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565			`8`
566			`wb`
567
568			`wb`
569			`0x00`
570
571
572			`mb_microbus`
573			`0x100`
574			`16`
575
576
577
578			`rb_dll_reg`
579			`0x0`
580			`8`
581			`read-only`
582
583
584
585			`tr_reg`
586			`0x0`
587			`8`
588			`write-strobe`
589
590
591
592
593			`ie_dlh_reg`
594			`0x1`
595			`8`
596			`read-only`
597
598
599
600			`ie_reg`
601			`0x1`
602			`4`
603			`write-strobe`
604
605
606
607
608			`dll_reg`
609			`0x0`
610			`8`
611			`write-strobe`
612
613
614
615
616			`dlh_reg`
617			`0x1`
618			`8`
619			`write-strobe`
620
621
622
623
624
625			`ii_reg`
626			`0x2`
627			`4`
628			`read-only`
629
630
631
632			`fc_reg`
633			`0x2`
634			`8`
635			`write-only`
636
637
638
639
640			`lc_reg`
641			`0x3`
642			`8`
643			`read-write`
644
645
646
647			`mc_reg`
648			`0x4`
649			`5`
650			`read-write`
651
652
653
654			`ls_reg`
655			`0x5`
656			`8`
657			`read-only`
658
659
660
661			`ms_reg`
662			`0x6`
663			`8`
664			`read-only`
665
666
667
668			`sr_reg`
669			`0x7`
670			`8`
671			`read-write`
672
673
674
675
676			`debug_0_reg`
677			`0x8`
678			`32`
679			`read-only`
680
681
682
683
684			`debug_1_reg`
685			`0xc`
686			`32`
687			`read-only`
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709