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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [wishbone/] [ip/] [wb_uart16550/] [rtl/] [xml/] [wb_uart16550_bus32_big.xml] - Blame information for rev 131

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xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
 
opencores.org
wishbone
wb_uart16550
bus32_big  default
 
 
 

 
 
 wb_clk
  
  
  
    
      
        clk
        wb_clk_i
      
    
 
 
 
 wb_reset
  
  
  
    
      
        reset
        wb_rst_i
      
    
 
 
 
 
 
wb
   
   
   big
   8
        
     
 
        
         adr
         
         wb_adr_i
           72
         
       
 
 
        
         wdata
         
         wb_dat_i
           310
         
       
 
 
        
         rdata
         
         wb_dat_o
           310
         
       
 
 
        
         sel
         
         wb_sel_i
           30
         
       
 
 
 
        
         ack
         
         wb_ack_o
         
       
 
 
        
         cyc
         
         wb_cyc_i
         
       
 
 
 
        
         stb
         
         wb_stb_i
         
       
 
 
        
         we
         
         wb_we_i
         
       
 
 
 
 
 
     
 

 

 
 
 
 
 
 

 
 

  gen_registers
  103.0
  none
  common
  ./tools/regtool/gen_registers
    
    
      bus_intf
      wb
    
    
      dest_dir
      ../verilog
    
  

 
 
 
 

  gen_verilog
  104.0
  none
  common
  ./tools/verilog/gen_verilog
  
    
      destination
      top.bus32_big
    
    
      dest_dir
      ../verilog
    
  

 
 
 
 
 
 

 
 
  
 
 
 
 
 
 
    
      fs-common
 
      
        
        ../verilog/top.body
        verilogSourcefragment
      
 
 
    
 
 
 
 
 
 
    
      fs-sim
 
      
        
        ../verilog/copyright.v
        verilogSourceinclude
      
 
      
        
        ../verilog/common/top.bus32_big
        verilogSourcemodule
      
 
 
 
      
        
        ../verilog/defines
        verilogSourceinclude
      
 
      
        wb
        ../verilog/wb_uart16550_bus32_big_wb
        verilogSourcemodule
      
 
 
 
      
        raminfr
        ../verilog/raminfr
        verilogSourcemodule
      
 
      
        receiver
        ../verilog/receiver
        verilogSourcemodule
      
 
      
        regs
        ../verilog/regs
        verilogSourcemodule
      
 
      
        rfifo
        ../verilog/rfifo
        verilogSourcemodule
      
 
      
        sync_flops
        ../verilog/sync_flops
        verilogSourcemodule
      
 
      
        tfifo
        ../verilog/tfifo
        verilogSourcemodule
      
 
      
        transmitter
        ../verilog/transmitter
        verilogSourcemodule
      
 
      
        wb_fsm
        ../verilog/wb_fsm
        verilogSourcemodule
      
 
 
 
 
    
 
 
    
      fs-syn
 
      
        
        ../verilog/copyright.v
        verilogSourceinclude
      
 
 
      
        
        ../verilog/common/top.bus32_big
        verilogSourcemodule
      
 
 
      
        
        ../verilog/defines
        verilogSourceinclude
      
 
      
        wb
        ../verilog/wb_uart16550_bus32_big_wb
        verilogSourcemodule
      
 
 
      
        raminfr
        ../verilog/raminfr
        verilogSourcemodule
      
 
      
        receiver
        ../verilog/receiver
        verilogSourcemodule
      
 
      
        regs
        ../verilog/regs
        verilogSourcemodule
      
 
      
        rfifo
        ../verilog/rfifo
        verilogSourcemodule
      
 
      
        sync_flops
        ../verilog/sync_flops
        verilogSourcemodule
      
 
      
        tfifo
        ../verilog/tfifo
        verilogSourcemodule
      
 
      
        transmitter
        ../verilog/transmitter
        verilogSourcemodule
      
 
      
        wb_fsm
        ../verilog/wb_fsm
        verilogSourcemodule
      
 
 
    
 
 
 
 
  
 
 
 
 
 

       
 
              
              verilog
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="verilog"/>
              
              
 
 
 
 
 
              
              commoncommon
 
              Verilog
              
                     
                            fs-common
                     
              
 
 
              
              sim:*Simulation:*
 
              Verilog
              
                     
                            fs-sim
                     
              
 
              
              syn:*Synthesis:*
 
              Verilog
              
                     
                            fs-syn
                     
              
 
 
              
              doc
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="documentation"/>
              
              :*Documentation:*
              Verilog
              
 
      
 
 
 
 

wb_addr_width8
wb_data_width32
wb_byte_lanes4
PRESCALER_PRESET16'h1234

 
 

 
baud_o
  wire
  out

 
cts_pad_i
  wire
  in

 
dcd_pad_i
  wire
  in

 
dsr_pad_i
  wire
  in

 
dtr_pad_o
  wire
  out

 
int_o
  wire
  out

 
 
ri_pad_i
  wire
  in

 
rts_pad_o
  wire
  out

 
srx_pad_i
  wire
  in

 
stx_pad_o
  wire
  out

 
 
 
 

 

 
 
 


8
 wb

 wb
 0x00
 
  
  mb_microbus
  0x100
  32
 
 
 
   rb_dll_reg
   0x0
   8
   read-only
  
 
 
   tr_reg
   0x0
   8
   write-strobe
  
 
 
 
   ie_dlh_reg
   0x1
   8
   read-only
  
 
 
   ie_reg
   0x1
   4
   write-strobe
  
 
 
 
   dll_reg
   0x0
   8
   write-strobe
  
 
 
 
   dlh_reg
   0x1
   8
   write-strobe
  
 
 
 
 
 
   ii_reg
   0x2
   4
   read-only
  
 
 
   fc_reg
   0x2
   8
   write-only
  
 
 
   lc_reg
   0x3
   8
   read-write
  
 
 
   mc_reg
   0x4
   5
   read-write
  
 
 
   ls_reg
   0x5
   8
   read-only
  
 
 
   ms_reg
   0x6
   8
   read-only
  
 
 
   sr_reg
   0x7
   8
   read-write
  
 
 
 

   debug_0_reg
   0x8
   32
   read-only
  
 
 

   debug_1_reg
   0xc
   32
   read-only
  
 
 
 
 
 
 
 
 
 
 
  
 
 

 

 
 
 
 


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Subversion Repositories socgen

[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [wishbone/] [ip/] [wb_uart16550/] [rtl/] [xml/] [wb_uart16550_bus32_big.xml] - Blame information for rev 131

Line No.	Rev	Author	Line
1	131	jt_eaton
2
30
31			`xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"`
32			`xmlns:socgen="http://opencores.org"`
33			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
34			`xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009`
35			`http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">`
36
37			`opencores.org`
38			`wishbone`
39			`wb_uart16550`
40			`bus32_big default`
41
42
43
44
45
46
47			`wb_clk`
48
49
50
51
52
53			`clk`
54			`wb_clk_i`
55
56
57
58
59
60			`wb_reset`
61
62
63
64
65
66			`reset`
67			`wb_rst_i`
68
69
70
71
72
73
74
75			`wb`
76
77
78			`big`
79			`8`
80
81
82
83
84			`adr`
85
86			`wb_adr_i`
87			`72`
88
89
90
91
92
93			`wdata`
94
95			`wb_dat_i`
96			`310`
97
98
99
100
101
102			`rdata`
103
104			`wb_dat_o`
105			`310`
106
107
108
109
110
111			`sel`
112
113			`wb_sel_i`
114			`30`
115
116
117
118
119
120
121			`ack`
122
123			`wb_ack_o`
124
125
126
127
128
129			`cyc`
130
131			`wb_cyc_i`
132
133
134
135
136
137
138			`stb`
139
140			`wb_stb_i`
141
142
143
144
145
146			`we`
147
148			`wb_we_i`
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171			`gen_registers`
172			`103.0`
173			`none`
174			`common`
175			`./tools/regtool/gen_registers`
176
177
178			`bus_intf`
179			`wb`
180
181
182			`dest_dir`
183			`../verilog`
184
185
186
187
188
189
190
191
192			`gen_verilog`
193			`104.0`
194			`none`
195			`common`
196			`./tools/verilog/gen_verilog`
197
198
199			`destination`
200			`top.bus32_big`
201
202
203			`dest_dir`
204			`../verilog`
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225			`fs-common`
226
227
228
229			`../verilog/top.body`
230			`verilogSourcefragment`
231
232
233
234
235
236
237
238
239
240
241
242			`fs-sim`
243
244
245
246			`../verilog/copyright.v`
247			`verilogSourceinclude`
248
249
250
251
252			`../verilog/common/top.bus32_big`
253			`verilogSourcemodule`
254
255
256
257
258
259
260			`../verilog/defines`
261			`verilogSourceinclude`
262
263
264
265			`wb`
266			`../verilog/wb_uart16550_bus32_big_wb`
267			`verilogSourcemodule`
268
269
270
271
272
273			`raminfr`
274			`../verilog/raminfr`
275			`verilogSourcemodule`
276
277
278
279			`receiver`
280			`../verilog/receiver`
281			`verilogSourcemodule`
282
283
284
285			`regs`
286			`../verilog/regs`
287			`verilogSourcemodule`
288
289
290
291			`rfifo`
292			`../verilog/rfifo`
293			`verilogSourcemodule`
294
295
296
297			`sync_flops`
298			`../verilog/sync_flops`
299			`verilogSourcemodule`
300
301
302
303			`tfifo`
304			`../verilog/tfifo`
305			`verilogSourcemodule`
306
307
308
309			`transmitter`
310			`../verilog/transmitter`
311			`verilogSourcemodule`
312
313
314
315			`wb_fsm`
316			`../verilog/wb_fsm`
317			`verilogSourcemodule`
318
319
320
321
322
323
324
325
326
327			`fs-syn`
328
329
330
331			`../verilog/copyright.v`
332			`verilogSourceinclude`
333
334
335
336
337
338			`../verilog/common/top.bus32_big`
339			`verilogSourcemodule`
340
341
342
343
344
345			`../verilog/defines`
346			`verilogSourceinclude`
347
348
349
350			`wb`
351			`../verilog/wb_uart16550_bus32_big_wb`
352			`verilogSourcemodule`
353
354
355
356
357			`raminfr`
358			`../verilog/raminfr`
359			`verilogSourcemodule`
360
361
362
363			`receiver`
364			`../verilog/receiver`
365			`verilogSourcemodule`
366
367
368
369			`regs`
370			`../verilog/regs`
371			`verilogSourcemodule`
372
373
374
375			`rfifo`
376			`../verilog/rfifo`
377			`verilogSourcemodule`
378
379
380
381			`sync_flops`
382			`../verilog/sync_flops`
383			`verilogSourcemodule`
384
385
386
387			`tfifo`
388			`../verilog/tfifo`
389			`verilogSourcemodule`
390
391
392
393			`transmitter`
394			`../verilog/transmitter`
395			`verilogSourcemodule`
396
397
398
399			`wb_fsm`
400			`../verilog/wb_fsm`
401			`verilogSourcemodule`
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420			`verilog`
421
422
423			`spirit:library="Testbench"`
424			`spirit:name="toolflow"`
425			`spirit:version="verilog"/>`
426
427
428
429
430
431
432
433
434			`commoncommon`
435
436			`Verilog`
437
438
439			`fs-common`
440
441
442
443
444
445			`sim:Simulation:`
446
447			`Verilog`
448
449
450			`fs-sim`
451
452
453
454
455			`syn:Synthesis:`
456
457			`Verilog`
458
459
460			`fs-syn`
461
462
463
464
465
466			`doc`
467
468
469			`spirit:library="Testbench"`
470			`spirit:name="toolflow"`
471			`spirit:version="documentation"/>`
472
473			`:Documentation:`
474			`Verilog`
475
476
477
478
479
480
481
482
483			`wb_addr_width8`
484			`wb_data_width32`
485			`wb_byte_lanes4`
486			`PRESCALER_PRESET16'h1234`
487
488
489
490
491
492			`baud_o`
493			`wire`
494			`out`
495
496
497			`cts_pad_i`
498			`wire`
499			`in`
500
501
502			`dcd_pad_i`
503			`wire`
504			`in`
505
506
507			`dsr_pad_i`
508			`wire`
509			`in`
510
511
512			`dtr_pad_o`
513			`wire`
514			`out`
515
516
517			`int_o`
518			`wire`
519			`out`
520
521
522
523			`ri_pad_i`
524			`wire`
525			`in`
526
527
528			`rts_pad_o`
529			`wire`
530			`out`
531
532
533			`srx_pad_i`
534			`wire`
535			`in`
536
537
538			`stx_pad_o`
539			`wire`
540			`out`
541
542
543
544
545
546
547
548
549
550
551
552
553
554			`8`
555			`wb`
556
557			`wb`
558			`0x00`
559
560
561			`mb_microbus`
562			`0x100`
563			`32`
564
565
566
567			`rb_dll_reg`
568			`0x0`
569			`8`
570			`read-only`
571
572
573
574			`tr_reg`
575			`0x0`
576			`8`
577			`write-strobe`
578
579
580
581
582			`ie_dlh_reg`
583			`0x1`
584			`8`
585			`read-only`
586
587
588
589			`ie_reg`
590			`0x1`
591			`4`
592			`write-strobe`
593
594
595
596
597			`dll_reg`
598			`0x0`
599			`8`
600			`write-strobe`
601
602
603
604
605			`dlh_reg`
606			`0x1`
607			`8`
608			`write-strobe`
609
610
611
612
613
614
615			`ii_reg`
616			`0x2`
617			`4`
618			`read-only`
619
620
621
622			`fc_reg`
623			`0x2`
624			`8`
625			`write-only`
626
627
628
629			`lc_reg`
630			`0x3`
631			`8`
632			`read-write`
633
634
635
636			`mc_reg`
637			`0x4`
638			`5`
639			`read-write`
640
641
642
643			`ls_reg`
644			`0x5`
645			`8`
646			`read-only`
647
648
649
650			`ms_reg`
651			`0x6`
652			`8`
653			`read-only`
654
655
656
657			`sr_reg`
658			`0x7`
659			`8`
660			`read-write`
661
662
663
664
665
666			`debug_0_reg`
667			`0x8`
668			`32`
669			`read-only`
670
671
672
673
674			`debug_1_reg`
675			`0xc`
676			`32`
677			`read-only`
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699