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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [wishbone/] [ip/] [wb_uart16550/] [sim/] [icarus/] [bus16_lit_default/] [wave.sav] - Blame information for rev 131

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Line No. Rev Author Line
1 131 jt_eaton 
[timestart] 0
2 
[size] 1613 999
3 
[pos] 785 13
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*-12.000000 6740 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
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[treeopen] TB.
6 
[treeopen] TB.test.
7 
[treeopen] TB.test.dut.
8 
[treeopen] TB.test.dut.regs.
9 
@28
10 
TB.test.cts_pad_i
11 
TB.test.dcd_pad_i
12 
TB.test.dsr_pad_i
13 
TB.test.ri_pad_i
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TB.test.dtr_pad_o
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TB.test.int_o
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TB.test.reset
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TB.test.rts_pad_o
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TB.test.srx_pad_i
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TB.test.stx_pad_o
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TB.test.wb_ack_o
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TB.test.wb_cyc_i
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@22
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TB.test.wb_sel_i[3:0]
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@28
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TB.test.wb_stb_i
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TB.test.wb_we_i
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@22
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TB.test.dut.wb_adr_i[7:0]
29 
@28
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TB.test.dut.wb_cyc_i
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@22
32 
TB.test.dut.micro_reg.fc_reg[7:0]
33 
TB.test.dut.micro_reg.ie_dlh_reg[7:0]
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TB.test.dut.micro_reg.rb_dll_reg[7:0]
35 
TB.test.dut.micro_reg.ii_reg[3:0]
36 
TB.test.dut.micro_reg.lc_reg[7:0]
37 
TB.test.dut.micro_reg.ls_reg[7:0]
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TB.test.dut.micro_reg.mc_reg[4:0]
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TB.test.dut.regs.ier[3:0]
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@28
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TB.test.dut.micro_reg.lc_reg_dec
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TB.test.dut.micro_reg.lc_reg_wr
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@22
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TB.test.dut.micro_reg.lc_reg[7:0]
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TB.test.dut.micro_reg.next_lc_reg[7:0]
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TB.test.dut.micro_reg.addr[7:0]
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TB.test.dut.micro_reg.wdata[15:0]
48 
@23
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TB.test.dut.regs.dl[15:0]
50 
[pattern_trace] 1
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[pattern_trace] 0

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