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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [wishbone/] [ip/] [wb_uart16550/] [sim/] [icarus/] [bus32_lit_default/] [wave.sav] - Blame information for rev 131

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Line No. Rev Author Line
1 131 jt_eaton 
[timestart] 3651188
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[size] 1613 999
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[pos] -1 -1
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*-6.000000 3651380 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
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[treeopen] TB.
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[treeopen] TB.test.
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@28
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TB.test.cts_pad_i
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TB.test.dcd_pad_i
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TB.test.dsr_pad_i
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TB.test.ri_pad_i
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TB.test.dtr_pad_o
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TB.test.int_o
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TB.test.reset
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TB.test.rts_pad_o
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TB.test.srx_pad_i
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TB.test.stx_pad_o
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TB.test.wb_ack_o
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TB.test.wb_cyc_i
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@22
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TB.test.wb_dat_i[31:0]
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TB.test.wb_sel_i[3:0]
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@28
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TB.test.wb_stb_i
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TB.test.wb_we_i
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@23
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TB.test.wb_dat_o[31:0]
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@22
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TB.test.dut.x[31:0]
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TB.test.dut.y[31:0]
31 
TB.test.dut.wb_adr_i[7:0]
32 
@28
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TB.test.dut.wb_cyc_i
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[pattern_trace] 1
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[pattern_trace] 0

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