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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [wishbone/] [ip/] [wb_uart16550/] [sim/] [icarus/] [default/] [wave.sav] - Blame information for rev 131

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Line No. Rev Author Line
1 131 jt_eaton 
[timestart] 3610713
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[size] 1613 999
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[pos] -1 -1
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*-7.000000 3611066 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
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[treeopen] TB.
6 
[treeopen] TB.test.
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[treeopen] TB.test.dut.
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[treeopen] TB.test.dut.regs.
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@28
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TB.test.wb_stb_i
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TB.test.wb_we_i
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TB.test.wb_cyc_i
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TB.test.wb_ack_o
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@22
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TB.test.dut.wb_dat8_o[7:0]
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TB.test.dut.regs.scratch[7:0]
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TB.test.dut.regs.wb_dat_i[7:0]
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TB.test.dut.regs.wb_dat_o[7:0]
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@28
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TB.test.dut.regs.tx_reset
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TB.test.dut.regs.start_dlc
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@22
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TB.test.dut.regs.rstate[3:0]
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TB.test.dut.regs.rf_data_out[10:0]
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TB.test.dut.regs.rf_count[4:0]
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TB.test.dut.regs.lsr[7:0]
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TB.test.dut.regs.lcr[7:0]
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@28
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TB.test.dut.regs.iir_read
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TB.test.dut.regs.enable
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TB.test.dut.regs.dlab
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@22
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TB.test.dut.regs.delayed_modem_signals[3:0]
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TB.test.dut.regs.block_cnt[7:0]
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TB.test.dut.regs.block_value[7:0]
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@28
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TB.test.dut.regs.baud_o
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@22
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TB.test.dut.regs.counter_t[9:0]
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@28
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TB.test.dut.regs.dcd_pad_i
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@22
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TB.test.dut.x[7:0]
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TB.test.dut.wb_dat_o[7:0]
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@28
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TB.test.dut.regs.wb_cyc_i
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@22
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TB.test.dut.regs.wb_dat_o[7:0]
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TB.test.dut.y[7:0]
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TB.test.dut.wb_adr_i[7:0]
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@28
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TB.test.dut.wb_cyc_i
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TB.test.dut.wb_stb_i
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TB.test.dut.wb_we_i
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TB.test.dut.wb_clk_i
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TB.test.dut.wb_ack_o
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@23
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TB.test.dut.rdata_rb_dll[7:0]
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[pattern_trace] 1
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[pattern_trace] 0

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