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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [wishbone/] [ip/] [wb_uart16550/] [sim/] [testbenches/] [verilog/] [tb.ext] - Blame information for rev 131

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reg  cts_pad_R;
reg  dcd_pad_R;
reg  dsr_pad_R;
reg  ri_pad_R;
 
 
assign   cts_pad_i   = cts_pad_R;
assign   dcd_pad_i   = dcd_pad_R;
assign   dsr_pad_i   = dsr_pad_R;
assign   ri_pad_i    = ri_pad_R;
 
assign wb_clk_i = clk;
assign wb_rst_i = reset;
 
assign STOP = 1'b0;
assign BAD = 1'b0;
 
 
 
 

Line No.	Rev	Author	Line
1	131	jt_eaton	`reg cts_pad_R;`
2			`reg dcd_pad_R;`
3			`reg dsr_pad_R;`
4			`reg ri_pad_R;`
5
6
7			`assign cts_pad_i = cts_pad_R;`
8			`assign dcd_pad_i = dcd_pad_R;`
9			`assign dsr_pad_i = dsr_pad_R;`
10			`assign ri_pad_i = ri_pad_R;`
11
12			`assign wb_clk_i = clk;`
13			`assign wb_rst_i = reset;`
14
15			`assign STOP = 1'b0;`
16			`assign BAD = 1'b0;`
17
18
19
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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [wishbone/] [ip/] [wb_uart16550/] [sim/] [testbenches/] [verilog/] [tb.ext] - Blame information for rev 131