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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [wishbone/] [ip/] [wb_uart16550/] [sim/] [testbenches/] [xml/] [wb_uart16550_bus16_big_tb.xml] - Blame information for rev 135

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xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014
http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">
 
opencores.org
wishbone
wb_uart16550
bus16_big_tb
 
 
 
 
 
 
 

 
 
 
 
 

  gen_verilog
  104.0
  none
  :*common:*
  tools/verilog/gen_verilog
    
    
      destination
      wb_uart16550_bus16_big_tb
    
  

 
 

 
 
 


    UART_MODEL_CLKCNT4'b1100
    UART_MODEL_SIZE4

 
 
 
 
       
 
 
              
              Params
 
              
              
                                   ipxact:library="wishbone"
                                   ipxact:name="wb_uart16550"
                                   ipxact:version="bus16_big_dut.params"/>
 
 
 
 
             
              
 
 
              
              Bfm
 
              
                                   ipxact:library="wishbone"
                                   ipxact:name="wb_uart16550"
                                   ipxact:version="bfm.design"/>
              
 
 
 
              
              icarus
              
              
                                   ipxact:library="Testbench"
                                   ipxact:name="toolflow"
                                   ipxact:version="icarus"/>
              
              
 
 
 
 
              
              headersheaders
 
              Verilog
              
              
 
 
              
              common:*common:*
              Verilog
              
                     
                            fs-common
                     
              
 
 
              
              sim:*Simulation:*
              Verilog
              
                     
                            fs-sim
                     
              
 
              
              lint:*Lint:*
              Verilog
              
                     
                            fs-lint
                     
              
 
 
      
 
 

 
  
 
 
    
      fs-common
 
      
        
        ../verilog/tb.ext
        verilogSourcefragment
      
 
    
 
 
 
 
 
 
 
 
    
      fs-sim
 
 
 
      
        
        ../verilog/common/wb_uart16550_bus16_big_tb
        verilogSourcemodule
      
 
 
 
 
 
 
    
 
 
    
      fs-lint
 
 
 
      
        
        ../verilog/common/wb_uart16550_bus16_big_tb
        verilogSourcemodule
      
 
 
 
 
 
 
    
 
 
 
 
 
 
  
 
 
 


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Subversion Repositories socgen

[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [wishbone/] [ip/] [wb_uart16550/] [sim/] [testbenches/] [xml/] [wb_uart16550_bus16_big_tb.xml] - Blame information for rev 135

Line No.	Rev	Author	Line
1	131	jt_eaton
2
30	135	jt_eaton
31			`xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"`
32	131	jt_eaton	`xmlns:socgen="http://opencores.org"`
33			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
34	135	jt_eaton	`xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014`
35			`http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">`
36	131	jt_eaton
37	135	jt_eaton	`opencores.org`
38			`wishbone`
39			`wb_uart16550`
40			`bus16_big_tb`
41	131	jt_eaton
42
43
44
45
46
47
48	135	jt_eaton
49	131	jt_eaton
50
51
52
53
54	135	jt_eaton
55			`gen_verilog`
56			`104.0`
57			`none`
58			`:common:`
59			`tools/verilog/gen_verilog`
60
61
62			`destination`
63			`wb_uart16550_bus16_big_tb`
64
65
66
67	131	jt_eaton
68
69	135	jt_eaton
70	131	jt_eaton
71
72
73	135	jt_eaton
74
75			`UART_MODEL_CLKCNT4'b1100`
76			`UART_MODEL_SIZE4`
77
78	131	jt_eaton
79
80
81
82	135	jt_eaton
83	131	jt_eaton
84
85	135	jt_eaton
86			`Params`
87	131	jt_eaton
88	135	jt_eaton
89
90			`ipxact:library="wishbone"`
91			`ipxact:name="wb_uart16550"`
92			`ipxact:version="bus16_big_dut.params"/>`
93	131	jt_eaton
94
95
96
97	135	jt_eaton
98
99	131	jt_eaton
100
101	135	jt_eaton
102			`Bfm`
103	131	jt_eaton
104	135	jt_eaton
105			`ipxact:library="wishbone"`
106			`ipxact:name="wb_uart16550"`
107			`ipxact:version="bfm.design"/>`
108
109	131	jt_eaton
110
111
112	135	jt_eaton
113			`icarus`
114
115
116			`ipxact:library="Testbench"`
117			`ipxact:name="toolflow"`
118			`ipxact:version="icarus"/>`
119
120
121	131	jt_eaton
122
123
124
125	135	jt_eaton
126			`headersheaders`
127	131	jt_eaton
128	135	jt_eaton	`Verilog`
129
130
131	131	jt_eaton
132
133	135	jt_eaton
134			`common:common:`
135			`Verilog`
136
137
138			`fs-common`
139
140
141	131	jt_eaton
142
143	135	jt_eaton
144			`sim:Simulation:`
145			`Verilog`
146
147
148			`fs-sim`
149
150
151	131	jt_eaton
152	135	jt_eaton
153			`lint:Lint:`
154			`Verilog`
155
156
157			`fs-lint`
158
159
160	131	jt_eaton
161
162	135	jt_eaton
163	131	jt_eaton
164
165	135	jt_eaton
166	131	jt_eaton
167	135	jt_eaton
168	131	jt_eaton
169
170	135	jt_eaton
171			`fs-common`
172	131	jt_eaton
173	135	jt_eaton
174
175			`../verilog/tb.ext`
176			`verilogSourcefragment`
177
178	131	jt_eaton
179	135	jt_eaton
180	131	jt_eaton
181
182
183
184
185
186
187
188	135	jt_eaton
189			`fs-sim`
190	131	jt_eaton
191
192
193	135	jt_eaton
194
195			`../verilog/common/wb_uart16550_bus16_big_tb`
196			`verilogSourcemodule`
197
198	131	jt_eaton
199
200
201
202
203
204	135	jt_eaton
205	131	jt_eaton
206
207	135	jt_eaton
208			`fs-lint`
209	131	jt_eaton
210
211
212	135	jt_eaton
213
214			`../verilog/common/wb_uart16550_bus16_big_tb`
215			`verilogSourcemodule`
216
217	131	jt_eaton
218
219
220
221
222
223	135	jt_eaton
224	131	jt_eaton
225
226
227
228
229
230	135	jt_eaton
231	131	jt_eaton
232
233
234	135	jt_eaton