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Subversion Repositories socgen

[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [wishbone/] [ip/] [wb_uart16550/] [sim/] [testbenches/] [xml/] [wb_uart16550_bus32_big_tb.xml] - Blame information for rev 131

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xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
 
opencores.org
wishbone
wb_uart16550
bus32_big_tb
 
 
 
 
 
 
 

 
 

  elab_verilog
  103.0
  none
  :*Simulation:*
  ./tools/verilog/elab_verilog

 

  trace_bus
  103.0
  none
  :*Simulation:*
  ./tools/verilog/trace_bus
    
    
      path
      root.dut
    
    
      bus_name
      wb
    
  

 
 
 
 
 

  gen_verilog
  104.0
  none
  common
  ./tools/verilog/gen_verilog
   
    
      destination
      top.bus32_big_tb
    
    
      dest_dir
      ../verilog
    
    
      top
    
  

 
 
 

 
 
 


    UART_MODEL_CLKCNT4'b1100
    UART_MODEL_SIZE4

 
 
 
       
 
 
              
              Params
 
              
                
                                   spirit:library="wishbone"
                                   spirit:name="wb_uart16550"
                                   spirit:version="bus32_big_dut.params"/>
 
 
 
 
             
              
 
 
              
              Bfm
 
              
                                   spirit:library="wishbone"
                                   spirit:name="wb_uart16550"
                                   spirit:version="bfm.design"/>
              
 
 
              
              icarus
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="icarus"/>
              
              
 
 
 
 
              
              headersheaders
 
              Verilog
              
              
 
              
              commoncommon
 
              Verilog
              
                     
                            fs-common
                     
              
 
 
 
              
              sim:*Simulation:*
 
              Verilog
              
                     
                            fs-sim
                     
              
 
              
              lint:*Lint:*
              Verilog
              
                     
                            fs-lint
                     
              
 
 
      
 
 
 
 
 

 
 
 
 
  
 
    
      fs-common
 
      
        
        ../verilog/tb.ext
        verilogSourcefragment
      
 
    
 
 
 
    
      fs-sim
 
      
        
        ../verilog/common/top.bus32_big_tb
        verilogSourcemodule
      
 
    
 
 
    
      fs-lint
 
      
        
        ../verilog/common/top.bus32_big_tb
        verilogSourcemodule
      
 
 
 
    
 
 
 
  
 
 
 


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Subversion Repositories socgen

[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [wishbone/] [ip/] [wb_uart16550/] [sim/] [testbenches/] [xml/] [wb_uart16550_bus32_big_tb.xml] - Blame information for rev 131

Line No.	Rev	Author	Line
1	131	jt_eaton
2
30
31			`xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"`
32			`xmlns:socgen="http://opencores.org"`
33			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
34			`xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009`
35			`http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">`
36
37			`opencores.org`
38			`wishbone`
39			`wb_uart16550`
40			`bus32_big_tb`
41
42
43
44
45
46
47
48
49
50
51
52			`elab_verilog`
53			`103.0`
54			`none`
55			`:Simulation:`
56			`./tools/verilog/elab_verilog`
57
58
59
60			`trace_bus`
61			`103.0`
62			`none`
63			`:Simulation:`
64			`./tools/verilog/trace_bus`
65
66
67			`path`
68			`root.dut`
69
70
71			`bus_name`
72			`wb`
73
74
75
76
77
78
79
80
81
82			`gen_verilog`
83			`104.0`
84			`none`
85			`common`
86			`./tools/verilog/gen_verilog`
87
88
89			`destination`
90			`top.bus32_big_tb`
91
92
93			`dest_dir`
94			`../verilog`
95
96
97			`top`
98
99
100
101
102
103
104
105
106
107
108
109
110			`UART_MODEL_CLKCNT4'b1100`
111			`UART_MODEL_SIZE4`
112
113
114
115
116
117
118
119
120			`Params`
121
122
123
124			`spirit:library="wishbone"`
125			`spirit:name="wb_uart16550"`
126			`spirit:version="bus32_big_dut.params"/>`
127
128
129
130
131
132
133
134
135
136			`Bfm`
137
138
139			`spirit:library="wishbone"`
140			`spirit:name="wb_uart16550"`
141			`spirit:version="bfm.design"/>`
142
143
144
145
146			`icarus`
147
148
149			`spirit:library="Testbench"`
150			`spirit:name="toolflow"`
151			`spirit:version="icarus"/>`
152
153
154
155
156
157
158
159			`headersheaders`
160
161			`Verilog`
162
163
164
165
166			`commoncommon`
167
168			`Verilog`
169
170
171			`fs-common`
172
173
174
175
176
177
178			`sim:Simulation:`
179
180			`Verilog`
181
182
183			`fs-sim`
184
185
186
187
188			`lint:Lint:`
189			`Verilog`
190
191
192			`fs-lint`
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211			`fs-common`
212
213
214
215			`../verilog/tb.ext`
216			`verilogSourcefragment`
217
218
219
220
221
222
223
224			`fs-sim`
225
226
227
228			`../verilog/common/top.bus32_big_tb`
229			`verilogSourcemodule`
230
231
232
233
234
235
236			`fs-lint`
237
238
239
240			`../verilog/common/top.bus32_big_tb`
241			`verilogSourcemodule`
242
243
244
245
246
247
248
249
250
251
252
253
254